+ iommu_as = g_malloc0(sizeof(AMDIOMMUAddressSpace *) *
PCI_DEVFN_MAX);
+ s->address_spaces[bus_num] = iommu_as;
+ }
+
+ /* set up IOMMU region */
+ if (!iommu_as[devfn]) {
+ iommu_as[devfn] = g_malloc0(sizeof(AMDIOMMUAddressSpace));
same here
+ iommu_as[devfn]->bus_num = (uint8_t)bus_num;
+ iommu_as[devfn]->devfn = (uint8_t)devfn;
+ iommu_as[devfn]->iommu_state = s;
+
+ memory_region_init_iommu(&iommu_as[devfn]->iommu, OBJECT(s),
+ &s->iommu_ops, "amd-iommu", UINT64_MAX);
+ address_space_init(&iommu_as[devfn]->as, &iommu_as[devfn]->iommu,
+ "amd-iommu");
+ }
+ return &iommu_as[devfn]->as;
+}
+
+/* validate a page table entry */
+static bool amd_iommu_validate_dte(AMDIOMMUState *s, uint16_t devid,
+ uint64_t *dte)
+{
+ if ((dte[0] & IOMMU_DTE_LOWER_QUAD_RESERVED)
+ || (dte[1] & IOMMU_DTE_MIDDLE_QUAD_RESERVED)
+ || (dte[2] & IOMMU_DTE_UPPER_QUAD_RESERVED) || dte[3]) {
+ amd_iommu_log_illegaldevtab_error(s, devid,
+ s->devtab + devid *
IOMMU_DEVTAB_ENTRY_SIZE, 0);
+ return false;
+ }
+
+ return dte[0] & IOMMU_DEV_VALID && (dte[0] &
IOMMU_DEV_TRANSLATION_VALID)
+ && (dte[0] & IOMMU_DEV_PT_ROOT_MASK);
+}
+
+/* get a device table entry given the devid */
+static bool amd_iommu_get_dte(AMDIOMMUState *s, int devid, uint64_t
*entry)
+{
+ uint32_t offset = devid * IOMMU_DEVTAB_ENTRY_SIZE;
+
+ IOMMU_DPRINTF(MMU, "Device Table at 0x%"PRIx64, s->devtab);
+
+ if (dma_memory_read(&address_space_memory, s->devtab + offset, entry,
+ IOMMU_DEVTAB_ENTRY_SIZE)) {
+ IOMMU_DPRINTF(MMU, "error: fail to access Device Entry devtab
0x%"PRIx64
+ "offset 0x%"PRIx32, s->devtab, offset);
+ /* log ever accessing dte */
+ amd_iommu_log_devtab_error(s, devid, s->devtab + offset, 0);
+ return false;
+ }
+
+ if (!amd_iommu_validate_dte(s, devid, entry)) {
+ IOMMU_DPRINTF(MMU,
+ "Pte entry at 0x%"PRIx64" is invalid", entry[0]);
+ return false;
+ }
+
+ return true;
+}
+
+/* get pte translation mode */
+static inline uint8_t get_pte_translation_mode(uint64_t pte)
+{
+ return (pte >> IOMMU_DEV_MODE_RSHIFT) & IOMMU_DEV_MODE_MASK;
+}
+
+static int amd_iommu_page_walk(AMDIOMMUAddressSpace *as, uint64_t *dte,
+ IOMMUTLBEntry *ret, unsigned perms,
+ hwaddr addr)
+{
+ uint8_t level, oldlevel;
+ unsigned present;
+ uint64_t pte, pte_addr;
+ uint64_t pte_perms;
+ pte = dte[0];
+
+ level = get_pte_translation_mode(pte);
+
+ if (level >= 7 || level == 0) {
+ IOMMU_DPRINTF(MMU, "error: translation level 0x%"PRIu8 "
detected"
+ "while translating 0x%"PRIx64, level, addr);
+ return -1;
+ }
+
+ while (level > 0) {
+ pte_perms = amd_iommu_get_perms(pte);
+ present = pte & 1;
+ if (!present || perms != (perms & pte_perms)) {
+ amd_iommu_page_fault(as->iommu_state, as->devfn, addr,
perms);
+ IOMMU_DPRINTF(MMU, "error: page fault accessing virtual addr
0x%"
+ PRIx64, addr);
+ return -1;
+ }
+
+ /* go to the next lower level */
+ pte_addr = pte & IOMMU_DEV_PT_ROOT_MASK;
+ /* add offset and load pte */
+ pte_addr += ((addr >> (3 + 9 * level)) & 0x1FF) << 3;
+ pte = ldq_phys(&address_space_memory, pte_addr);
+ oldlevel = level;
+ level = get_pte_translation_mode(pte);
+
+ /* PT is corrupted or not there */
+ if (level != oldlevel - 1) {
+ return -1;
+ }
+ }
+
+ ret->iova = addr & IOMMU_PAGE_MASK_4K;
+ ret->translated_addr = (pte & IOMMU_DEV_PT_ROOT_MASK) &
IOMMU_PAGE_MASK_4K;
+ ret->addr_mask = ~IOMMU_PAGE_MASK_4K;
+ ret->perm = IOMMU_RW;
+ return 0;
+}
+
+/* TODO : Mark addresses as Accessed and Dirty */
If you don't mark addresses as dirty, can't this cause the sporadic errors
of arbitrary programs Jan talked about?
+static void amd_iommu_do_translate(AMDIOMMUAddressSpace *as, hwaddr addr,
+ bool is_write, IOMMUTLBEntry *ret)
+{
+ AMDIOMMUState *s = as->iommu_state;
+ uint16_t devid = PCI_DEVID(as->bus_num, as->devfn);
+ IOMMUIOTLBEntry *iotlb_entry;
+ uint8_t err;
+ uint64_t entry[4];
+
+ /* try getting a cache entry first */
+ iotlb_entry = amd_iommu_iotlb_lookup(s, addr, as->devfn);
+
+ if (iotlb_entry) {
+ IOMMU_DPRINTF(CACHE, "hit iotlb devid: %02x:%02x.%x gpa
0x%"PRIx64
+ " hpa 0x%"PRIx64, PCI_BUS_NUM(devid),
PCI_SLOT(devid),
+ PCI_FUNC(devid), addr,
iotlb_entry->translated_addr);
+ ret->iova = addr & IOMMU_PAGE_MASK_4K;
+ ret->translated_addr = iotlb_entry->translated_addr;
+ ret->addr_mask = ~IOMMU_PAGE_MASK_4K;
+ ret->perm = iotlb_entry->perms;
+ return;
+ } else {
you return from the if clause so you don't need the else
+ if (!amd_iommu_get_dte(s, devid, entry)) {
is not an error if you did not find the device id?
+ goto out;
+ }
+
+ err = amd_iommu_page_walk(as, entry, ret,
+ is_write ? IOMMU_PERM_WRITE :
IOMMU_PERM_READ,
+ addr);
+ if (err) {
+ IOMMU_DPRINTF(MMU, "error: hardware error accessing page
tables"
+ " while translating addr 0x%"PRIx64, addr);
+ amd_iommu_log_pagetab_error(s, as->devfn, addr, 0);
+ goto out;
+ }
+
+ amd_iommu_update_iotlb(s, as->devfn, addr, ret->translated_addr,
+ ret->perm, entry[1] &
IOMMU_DEV_DOMID_ID_MASK);
+ return;
+ }
+
+out:
+ ret->iova = addr;
+ ret->translated_addr = addr & IOMMU_PAGE_MASK_4K;
+ ret->addr_mask = ~IOMMU_PAGE_MASK_4K;
+ ret->perm = IOMMU_RW;
+ return;
you don't need the above return
+}
+
+static IOMMUTLBEntry amd_iommu_translate(MemoryRegion *iommu, hwaddr
addr,
+ bool is_write)
+{
+ IOMMU_DPRINTF(GENERAL, "");
+
+ AMDIOMMUAddressSpace *as = container_of(iommu, AMDIOMMUAddressSpace,
iommu);
+ AMDIOMMUState *s = as->iommu_state;
+
+ IOMMUTLBEntry ret = {
+ .target_as = &address_space_memory,
+ .iova = addr,
+ .translated_addr = 0,
+ .addr_mask = ~(hwaddr)0,
+ .perm = IOMMU_NONE,
+ };
+
+ if (!s->enabled) {
+ /* IOMMU disabled - corresponds to iommu=off not
+ * failure to provide any parameter
+ */
+ ret.iova = addr & IOMMU_PAGE_MASK_4K;
+ ret.translated_addr = addr & IOMMU_PAGE_MASK_4K;
+ ret.addr_mask = ~IOMMU_PAGE_MASK_4K;
+ ret.perm = IOMMU_RW;
+ return ret;
+ }
+
+ amd_iommu_do_translate(as, addr, is_write, &ret);
+ IOMMU_DPRINTF(MMU, "devid: %02x:%02x.%x gpa 0x%"PRIx64 " hpa
0x%"PRIx64,
+ as->bus_num, PCI_SLOT(as->devfn), PCI_FUNC(as->devfn),
addr,
+ ret.translated_addr);
+
+ return ret;
+}
+
+static const MemoryRegionOps mmio_mem_ops = {
+ .read = amd_iommu_mmio_read,
+ .write = amd_iommu_mmio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ .unaligned = false,
+ },
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ }
+};
+
+static void amd_iommu_init(AMDIOMMUState *s)
+{
+ printf("amd_iommu_init");
you should use the debug macro here
+
+ amd_iommu_iotlb_reset(s);
+
+ s->iommu_ops.translate = amd_iommu_translate;
+
+ s->devtab_len = 0;
+ s->cmdbuf_len = 0;
+ s->cmdbuf_head = 0;
+ s->cmdbuf_tail = 0;
+ s->evtlog_head = 0;
+ s->evtlog_tail = 0;
+ s->excl_enabled = false;
+ s->excl_allow = false;
+ s->mmio_enabled = false;
+ s->enabled = false;
+ s->ats_enabled = false;
+ s->cmdbuf_enabled = false;
+
+ /* reset MMIO */
+ memset(s->mmior, 0, IOMMU_MMIO_SIZE);
+ amd_iommu_set_quad(s, IOMMU_MMIO_EXT_FEATURES, IOMMU_EXT_FEATURES,
+ 0xffffffffffffffef, 0);
+ amd_iommu_set_quad(s, IOMMU_MMIO_STATUS, 0, 0x98, 0x67);
+ /* reset device ident */
+ pci_config_set_vendor_id(s->dev.config, PCI_VENDOR_ID_AMD);
+ pci_config_set_device_id(s->dev.config, PCI_DEVICE_ID_RD890_IOMMU);
+ pci_config_set_prog_interface(s->dev.config, 00);
+ pci_config_set_class(s->dev.config, 0x0806);
+
+ /* reset IOMMU specific capabilities */
+ pci_set_long(s->dev.config + s->capab_offset, IOMMU_CAPAB_FEATURES);
+ pci_set_long(s->dev.config + s->capab_offset + IOMMU_CAPAB_BAR_LOW,
+ s->mmio.addr & ~(0xffff0000));
+ pci_set_long(s->dev.config + s->capab_offset + IOMMU_CAPAB_BAR_HIGH,
+ (s->mmio.addr & ~(0xffff)) >> 16);
+ pci_set_long(s->dev.config + s->capab_offset + IOMMU_CAPAB_RANGE,
+ 0xff000000);
+ pci_set_long(s->dev.config + s->capab_offset + IOMMU_CAPAB_MISC, 0);
+ pci_set_long(s->dev.config + s->capab_offset + IOMMU_CAPAB_MISC,
+ IOMMU_MAX_PH_ADDR | IOMMU_MAX_GVA_ADDR | IOMMU_MAX_VA_ADDR);
All the capabilities are read-write? Otherwise you need to set the wmask
to indicate what fields are writable.
+}
+
+static void amd_iommu_reset(DeviceState *dev)
+{
+ AMDIOMMUState *s = AMD_IOMMU_DEVICE(dev);
+
+ amd_iommu_init(s);
+}
+
+static void amd_iommu_realize(PCIDevice *dev, Error **error)
+{
+ AMDIOMMUState *s = container_of(dev, AMDIOMMUState, dev);
+
+ s->iotlb = g_hash_table_new_full(amd_iommu_uint64_hash,
+ amd_iommu_uint64_equal, g_free,
g_free);
+
+ s->capab_offset = pci_add_capability(dev, IOMMU_CAPAB_ID_SEC, 0,
+ IOMMU_CAPAB_SIZE);
+
+ /* add msi and hypertransport capabilities */
+ pci_add_capability(&s->dev, PCI_CAP_ID_MSI, 0, IOMMU_CAPAB_REG_SIZE);
+ pci_add_capability(&s->dev, PCI_CAP_ID_HT, 0, IOMMU_CAPAB_REG_SIZE);
+
+ amd_iommu_init(s);
+
+ /* set up MMIO */
+ memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "mmio",
+ IOMMU_MMIO_SIZE);
+
+ if (s->mmio.addr == IOMMU_BASE_ADDR) {
I don't understand why is need here. realize is called only once in the init
process
and you set it a few lines below.
+ return;
+ }
+
+ s->mmio.addr = IOMMU_BASE_ADDR;
+ memory_region_add_subregion(get_system_memory(), IOMMU_BASE_ADDR,
&s->mmio);
+}
+
+static const VMStateDescription vmstate_amd_iommu = {
+ .name = "amd-iommu",
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(dev, AMDIOMMUState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property amd_iommu_properties[] = {
+ DEFINE_PROP_UINT32("version", AMDIOMMUState, version, 2),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void amd_iommu_uninit(PCIDevice *dev)
+{
+ AMDIOMMUState *s = container_of(dev, AMDIOMMUState, dev);
+ amd_iommu_iotlb_reset(s);
at this point you also need to clean also the memory regions you use.
+}
+
+static void amd_iommu_class_init(ObjectClass *klass, void* data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->realize = amd_iommu_realize;
+ k->exit = amd_iommu_uninit;
+
+ dc->reset = amd_iommu_reset;
+ dc->vmsd = &vmstate_amd_iommu;
+ dc->props = amd_iommu_properties;
+}
+
+static const TypeInfo amd_iommu = {
+ .name = TYPE_AMD_IOMMU_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(AMDIOMMUState),
+ .class_init = amd_iommu_class_init
+};
+
+static void amd_iommu_register_types(void)
+{
+ type_register_static(&amd_iommu);
+}
+
+type_init(amd_iommu_register_types);
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
new file mode 100644
index 0000000..7d317e1
--- /dev/null
+++ b/hw/i386/amd_iommu.h
@@ -0,0 +1,395 @@
+/*
+ * QEMU emulation of an AMD IOMMU (AMD-Vi)
+ *
+ * Copyright (C) 2011 Eduard - Gabriel Munteanu
+ * Copyright (C) 2015 David Kiarie, <address@hidden>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef AMD_IOMMU_H_
+#define AMD_IOMMU_H_
+
+#include "hw/hw.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/msi.h"
+#include "hw/sysbus.h"
+#include "sysemu/dma.h"
+
+/* Capability registers */
+#define IOMMU_CAPAB_HEADER 0x00
+#define IOMMU_CAPAB_REV_TYPE 0x02
+#define IOMMU_CAPAB_FLAGS 0x03
+#define IOMMU_CAPAB_BAR_LOW 0x04
+#define IOMMU_CAPAB_BAR_HIGH 0x08
+#define IOMMU_CAPAB_RANGE 0x0C
+#define IOMMU_CAPAB_MISC 0x10
+#define IOMMU_CAPAB_MISC1 0x14
+
+#define IOMMU_CAPAB_SIZE 0x18
+#define IOMMU_CAPAB_REG_SIZE 0x04
+
+/* Capability header data */
+#define IOMMU_CAPAB_ID_SEC 0xf
+#define IOMMU_CAPAB_FLAT_EXT (1 << 28)
+#define IOMMU_CAPAB_EFR_SUP (1 << 27)
+#define IOMMU_CAPAB_FLAG_NPCACHE (1 << 26)
+#define IOMMU_CAPAB_FLAG_HTTUNNEL (1 << 25)
+#define IOMMU_CAPAB_FLAG_IOTLBSUP (1 << 24)
+#define IOMMU_CAPAB_INIT_REV (1 << 19)
+#define IOMMU_CAPAB_INIT_TYPE (3 << 16)
+#define IOMMU_CAPAB_INIT_REV_TYPE (IOMMU_CAPAB_REV |
IOMMU_CAPAB_TYPE)
+#define IOMMU_CAPAB_INIT_FLAGS (IOMMU_CAPAB_FLAG_NPCACHE | \
+ IOMMU_CAPAB_FLAG_HTTUNNEL)
+#define IOMMU_CAPAB_INIT_MISC ((64 << 15) | (48 << 8))
+#define IOMMU_CAPAB_BAR_MASK (~((1UL << 14) - 1))
+
+/* MMIO registers */
+#define IOMMU_MMIO_DEVICE_TABLE 0x0000
+#define IOMMU_MMIO_COMMAND_BASE 0x0008
+#define IOMMU_MMIO_EVENT_BASE 0x0010
+#define IOMMU_MMIO_CONTROL 0x0018
+#define IOMMU_MMIO_EXCL_BASE 0x0020
+#define IOMMU_MMIO_EXCL_LIMIT 0x0028
+#define IOMMU_MMIO_EXT_FEATURES 0x0030
+#define IOMMU_MMIO_COMMAND_HEAD 0x2000
+#define IOMMU_MMIO_COMMAND_TAIL 0x2008
+#define IOMMU_MMIO_EVENT_HEAD 0x2010
+#define IOMMU_MMIO_EVENT_TAIL 0x2018
+#define IOMMU_MMIO_STATUS 0x2020
+#define IOMMU_MMIO_PPR_BASE 0x0038
+#define IOMMU_MMIO_PPR_HEAD 0x2030
+#define IOMMU_MMIO_PPR_TAIL 0x2038
+
+#define IOMMU_MMIO_SIZE 0x4000
+
+#define IOMMU_MMIO_DEVTAB_SIZE_MASK ((1ULL << 12) - 1)
+#define IOMMU_MMIO_DEVTAB_BASE_MASK (((1ULL << 52) - 1) & ~ \
+ IOMMU_MMIO_DEVTAB_SIZE_MASK)
+#define IOMMU_MMIO_DEVTAB_ENTRY_SIZE 32
+#define IOMMU_MMIO_DEVTAB_SIZE_UNIT 4096
+
+/* some of this are similar but just for readability */
+#define IOMMU_MMIO_CMDBUF_SIZE_BYTE (IOMMU_MMIO_COMMAND_BASE + 7)
+#define IOMMU_MMIO_CMDBUF_SIZE_MASK 0x0F
+#define IOMMU_MMIO_CMDBUF_BASE_MASK IOMMU_MMIO_DEVTAB_BASE_MASK
+#define IOMMU_MMIO_CMDBUF_DEFAULT_SIZE 8
+#define IOMMU_MMIO_CMDBUF_HEAD_MASK (((1ULL << 19) - 1) & ~0x0F)
+#define IOMMU_MMIO_CMDBUF_TAIL_MASK IOMMU_MMIO_EVTLOG_HEAD_MASK
+
+#define IOMMU_MMIO_EVTLOG_SIZE_BYTE (IOMMU_MMIO_EVENT_BASE + 7)
+#define IOMMU_MMIO_EVTLOG_SIZE_MASK IOMMU_MMIO_CMDBUF_SIZE_MASK
+#define IOMMU_MMIO_EVTLOG_BASE_MASK IOMMU_MMIO_CMDBUF_BASE_MASK
+#define IOMMU_MMIO_EVTLOG_DEFAULT_SIZE IOMMU_MMIO_CMDBUF_DEFAULT_SIZE
+#define IOMMU_MMIO_EVTLOG_HEAD_MASK (((1ULL << 19) - 1) & ~0x0F)
+#define IOMMU_MMIO_EVTLOG_TAIL_MASK IOMMU_MMIO_EVTLOG_HEAD_MASK
+
+#define IOMMU_MMIO_PPRLOG_SIZE_BYTE (IOMMU_MMIO_EVENT_BASE + 7)
+#define IOMMU_MMIO_PPRLOG_HEAD_MASK IOMMU_MMIO_EVTLOG_HEAD_MASK
+#define IOMMU_MMIO_PPRLOG_TAIL_MASK IOMMU_MMIO_EVTLOG_HEAD_MASK
+#define IOMMU_MMIO_PPRLOG_BASE_MASK IOMMU_MMIO_EVTLOG_BASE_MASK
+#define IOMMU_MMIO_PPRLOG_SIZE_MASK IOMMU_MMIO_EVTLOG_SIZE_MASK
+
+#define IOMMU_MMIO_EXCL_BASE_MASK IOMMU_MMIO_DEVTAB_BASE_MASK
+#define IOMMU_MMIO_EXCL_ENABLED_MASK (1ULL << 0)
+#define IOMMU_MMIO_EXCL_ALLOW_MASK (1ULL << 1)
+#define IOMMU_MMIO_EXCL_LIMIT_MASK IOMMU_MMIO_DEVTAB_BASE_MASK
+#define IOMMU_MMIO_EXCL_LIMIT_LOW 0xFFF
+
+/* mmio control register flags */
+#define IOMMU_MMIO_CONTROL_IOMMUEN (1ULL << 0)
+#define IOMMU_MMIO_CONTROL_HTTUNEN (1ULL << 1)
+#define IOMMU_MMIO_CONTROL_EVENTLOGEN (1ULL << 2)
+#define IOMMU_MMIO_CONTROL_EVENTINTEN (1ULL << 3)
+#define IOMMU_MMIO_CONTROL_COMWAITINTEN (1ULL << 4)
+#define IOMMU_MMIO_CONTROL_PASSPW (1ULL << 7)
+#define IOMMU_MMIO_CONTROL_REPASSPW (1ULL << 9)
+#define IOMMU_MMIO_CONTROL_COHERENT (1ULL << 10)
+#define IOMMU_MMIO_CONTROL_ISOC (1ULL << 11)
+#define IOMMU_MMIO_CONTROL_CMDBUFLEN (1ULL << 12)
+#define IOMMU_MMIO_CONTROL_PPRLOGEN (1ULL << 13)
+#define IOMMU_MMIO_CONTROL_PPRINTEN (1ULL << 14)
+#define IOMMU_MMIO_CONTROL_PPREN (1ULL << 15)
+#define IOMMU_MMIO_CONTROL_GAEN (1ULL << 16)
+#define IOMMU_MMIO_CONTROL_GTEN (1ULL << 17)
+
+/* MMIO status register bits */
+#define IOMMU_MMIO_STATUS_PPR_OVFE (1 << 18)
+#define IOMMU_MMIO_STATUS_PPR_OVFEB (1 << 17)
+#define IOMMU_MMIO_STATUS_EVT_ACTIVE (1 << 16)
+#define IOMMU_MMIO_STATUS_EVT_OVFB (1 << 15)
+#define IOMMU_MMIO_STATUS_PPR_ACTIVE (1 << 12)
+#define IOMMU_MMIO_STATUS_PPR_OVFB (1 << 11)
+#define IOMMU_MMIO_STATUS_GA_INT (1 << 10)
+#define IOMMU_MMIO_STATUS_GA_RUN (1 << 9)
+#define IOMMU_MMIO_STATUS_GA_OVF (1 << 8)
+#define IOMMU_MMIO_STATUS_PPR_RUN (1 << 7)
+#define IOMMU_MMIO_STATUS_PPR_INT (1 << 6)
+#define IOMMU_MMIO_STATUS_PPR_OVF (1 << 5)
+#define IOMMU_MMIO_STATUS_CMDBUF_RUN (1 << 4)
+#define IOMMU_MMIO_STATUS_EVT_RUN (1 << 3)
+#define IOMMU_MMIO_STATUS_COMP_INT (1 << 2)
+#define IOMMU_MMIO_STATUS_EVT_INT (1 << 1)
+#define IOMMU_MMIO_STATUS_EVT_OVF (1 << 0)
+
+#define IOMMU_CMDBUF_ID_BYTE 0x07
+#define IOMMU_CMDBUF_ID_RSHIFT 4
+
+#define IOMMU_CMD_COMPLETION_WAIT 0x01
+#define IOMMU_CMD_INVAL_DEVTAB_ENTRY 0x02
+#define IOMMU_CMD_INVAL_IOMMU_PAGES 0x03
+#define IOMMU_CMD_INVAL_IOTLB_PAGES 0x04
+#define IOMMU_CMD_INVAL_INTR_TABLE 0x05
+#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
+#define IOMMU_CMD_COMPLETE_PPR_REQUEST 0x07
+#define IOMMU_CMD_INVAL_IOMMU_ALL 0x08
+
+#define IOMMU_DEVTAB_ENTRY_SIZE 32
+
+/* Device table entry bits 0:63 */
+#define IOMMU_DEV_VALID (1ULL << 0)
+#define IOMMU_DEV_TRANSLATION_VALID (1ULL << 1)
+#define IOMMU_DEV_MODE_MASK 0x7
+#define IOMMU_DEV_MODE_RSHIFT 9
+#define IOMMU_DEV_PT_ROOT_MASK 0xFFFFFFFFFF000
+#define IOMMU_DEV_PT_ROOT_RSHIFT 12
+#define IOMMU_DEV_PERM_SHIFT 61
+#define IOMMU_DEV_PERM_READ (1ULL << 61)
+#define IOMMU_DEV_PERM_WRITE (1ULL << 62)
+
+/* Device table entry bits 64:127 */
+#define IOMMU_DEV_DOMID_ID_MASK ((1ULL << 16) - 1)
+#define IOMMU_DEV_IOTLB_SUPPORT (1ULL << 17)
+#define IOMMU_DEV_SUPPRESS_PF (1ULL << 18)
+#define IOMMU_DEV_SUPPRESS_ALL_PF (1ULL << 19)
+#define IOMMU_DEV_IOCTL_MASK (~3)
+#define IOMMU_DEV_IOCTL_RSHIFT 20
+#define IOMMU_DEV_IOCTL_DENY 0
+#define IOMMU_DEV_IOCTL_PASSTHROUGH 1
+#define IOMMU_DEV_IOCTL_TRANSLATE 2
+#define IOMMU_DEV_CACHE (1ULL << 37)
+#define IOMMU_DEV_SNOOP_DISABLE (1ULL << 38)
+#define IOMMU_DEV_EXCL (1ULL << 39)
+
+/* Event codes and flags, as stored in the info field */
+#define IOMMU_EVENT_ILLEGAL_DEVTAB_ENTRY (0x1U << 12)
+#define IOMMU_EVENT_IOPF (0x2U << 12)
+#define IOMMU_EVENT_IOPF_I (1U << 3)
+#define IOMMU_EVENT_IOPF_PR (1U << 4)
+#define IOMMU_EVENT_IOPF_RW (1U << 5)
+#define IOMMU_EVENT_IOPF_PE (1U << 6)
+#define IOMMU_EVENT_IOPF_RZ (1U << 7)
+#define IOMMU_EVENT_IOPF_TR (1U << 8)
+#define IOMMU_EVENT_DEV_TAB_HW_ERROR (0x3U << 12)
+#define IOMMU_EVENT_PAGE_TAB_HW_ERROR (0x4U << 12)
+#define IOMMU_EVENT_ILLEGAL_COMMAND_ERROR (0x5U << 12)
+#define IOMMU_EVENT_COMMAND_HW_ERROR (0x6U << 12)
+#define IOMMU_EVENT_IOTLB_INV_TIMEOUT (0x7U << 12)
+#define IOMMU_EVENT_INVALID_DEV_REQUEST (0x8U << 12)
+
+#define IOMMU_EVENT_LEN 16
+#define IOMMU_PERM_READ (1 << 0)
+#define IOMMU_PERM_WRITE (1 << 1)
+#define IOMMU_PERM_RW (IOMMU_PERM_READ | IOMMU_PERM_WRITE)
+
+/* AMD RD890 Chipset */
+#define PCI_DEVICE_ID_RD890_IOMMU 0x20