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Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR
From: |
Thomas Huth |
Subject: |
Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR |
Date: |
Wed, 16 Mar 2016 07:24:01 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 |
On 16.03.2016 02:14, David Gibson wrote:
> On Mon, Mar 14, 2016 at 05:56:39PM +0100, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <address@hidden>
>>
>> We should implement HW breakpoint/watchpoint, qemu supports them...
>>
>> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
>
> Reviewed-by: David Gibson <address@hidden>
>
> But I'm assuming 2.7, not 2.6.
Looks like this register can be set by the guest using the H_SET_MODE
hypercall, too (search for H_SET_MODE_RESOURCE_SET_CIABR in the KVM
kernel sources), similar to the DAWR register.
And this patch is using KVM_REG_PPC_CIABR to link this register with the
KVM code in the kernel ... so I think this patch should still go into
2.6 to make sure that the register is migrated properly.
Thomas
>> ---
>> target-ppc/cpu.h | 1 +
>> target-ppc/translate_init.c | 5 +++++
>> 2 files changed, 6 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 5203cc6a3bfb..9e1ef10b7dc6 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env,
>> bool ifetch)
>> #define SPR_DAWR (0x0B4)
>> #define SPR_MPPR (0x0B8)
>> #define SPR_RPR (0x0BA)
>> +#define SPR_CIABR (0x0BB)
>> #define SPR_DAWRX (0x0BC)
>> #define SPR_HFSCR (0x0BE)
>> #define SPR_VRSAVE (0x100)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index cfb1bc088950..f88bdf7b3cd1 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
>> SPR_NOACCESS, SPR_NOACCESS,
>> &spr_read_generic, &spr_write_generic,
>> KVM_REG_PPC_DAWRX, 0x00000000);
>> + spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + KVM_REG_PPC_CIABR, 0x00000000);
>> }
>>
>> static void gen_spr_970_dbg(CPUPPCState *env)
>
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- Re: [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s, (continued)
[Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV, Cédric Le Goater, 2016/03/14
[Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR, Cédric Le Goater, 2016/03/14
[Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8, Cédric Le Goater, 2016/03/14
[Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged, Cédric Le Goater, 2016/03/14
[Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB, Cédric Le Goater, 2016/03/14