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[Qemu-devel] [PATCH 08/49] target-i386: make cpu-qom.h not target specif
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PATCH 08/49] target-i386: make cpu-qom.h not target specific |
Date: |
Wed, 16 Mar 2016 11:46:18 +0100 |
Make X86CPU an opaque type within cpu-qom.h, and move all definitions of
private methods, as well as all type definitions that require knowledge
of the layout to cpu.h. This helps making files independent of NEED_CPU_H
if they only need to pass around CPU pointers.
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-i386/cpu-qom.h | 97 +-------------------------------------------------
target-i386/cpu.h | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 98 insertions(+), 97 deletions(-)
diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index 2ca7b9e..5dde658 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -67,101 +67,6 @@ typedef struct X86CPUClass {
void (*parent_reset)(CPUState *cpu);
} X86CPUClass;
-/**
- * X86CPU:
- * @env: #CPUX86State
- * @migratable: If set, only migratable flags will be accepted when "enforce"
- * mode is used, and only migratable flags will be included in the "host"
- * CPU model.
- *
- * An x86 CPU.
- */
-typedef struct X86CPU {
- /*< private >*/
- CPUState parent_obj;
- /*< public >*/
-
- CPUX86State env;
-
- bool hyperv_vapic;
- bool hyperv_relaxed_timing;
- int hyperv_spinlock_attempts;
- char *hyperv_vendor_id;
- bool hyperv_time;
- bool hyperv_crash;
- bool hyperv_reset;
- bool hyperv_vpindex;
- bool hyperv_runtime;
- bool hyperv_synic;
- bool hyperv_stimer;
- bool check_cpuid;
- bool enforce_cpuid;
- bool expose_kvm;
- bool migratable;
- bool host_features;
- int64_t apic_id;
-
- /* if true the CPUID code directly forward host cache leaves to the guest
*/
- bool cache_info_passthrough;
-
- /* Features that were filtered out because of missing host capabilities */
- uint32_t filtered_features[FEATURE_WORDS];
-
- /* Enable PMU CPUID bits. This can't be enabled by default yet because
- * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
- * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
- * capabilities) directly to the guest.
- */
- bool enable_pmu;
-
- /* in order to simplify APIC support, we leave this pointer to the
- user */
- struct DeviceState *apic_state;
- struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
- Notifier machine_done;
-} X86CPU;
-
-static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
-{
- return container_of(env, X86CPU, env);
-}
-
-#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
-
-#define ENV_OFFSET offsetof(X86CPU, env)
-
-#ifndef CONFIG_USER_ONLY
-extern struct VMStateDescription vmstate_x86_cpu;
-#endif
-
-/**
- * x86_cpu_do_interrupt:
- * @cpu: vCPU the interrupt is to be handled by.
- */
-void x86_cpu_do_interrupt(CPUState *cpu);
-bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
-
-int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
-int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
-int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
-void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
-
-void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
- int flags);
-
-hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-
-int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
-int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-
-void x86_cpu_exec_enter(CPUState *cpu);
-void x86_cpu_exec_exit(CPUState *cpu);
+typedef struct X86CPU X86CPU;
#endif
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 5148c82..c2f4af4 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -20,6 +20,7 @@
#define CPU_I386_H
#include "qemu-common.h"
+#include "cpu-qom.h"
#include "standard-headers/asm-x86/hyperv.h"
#ifdef TARGET_X86_64
@@ -1024,7 +1025,102 @@ typedef struct CPUX86State {
TPRAccess tpr_access_type;
} CPUX86State;
-#include "cpu-qom.h"
+/**
+ * X86CPU:
+ * @env: #CPUX86State
+ * @migratable: If set, only migratable flags will be accepted when "enforce"
+ * mode is used, and only migratable flags will be included in the "host"
+ * CPU model.
+ *
+ * An x86 CPU.
+ */
+struct X86CPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUX86State env;
+
+ bool hyperv_vapic;
+ bool hyperv_relaxed_timing;
+ int hyperv_spinlock_attempts;
+ char *hyperv_vendor_id;
+ bool hyperv_time;
+ bool hyperv_crash;
+ bool hyperv_reset;
+ bool hyperv_vpindex;
+ bool hyperv_runtime;
+ bool hyperv_synic;
+ bool hyperv_stimer;
+ bool check_cpuid;
+ bool enforce_cpuid;
+ bool expose_kvm;
+ bool migratable;
+ bool host_features;
+ int64_t apic_id;
+
+ /* if true the CPUID code directly forward host cache leaves to the guest
*/
+ bool cache_info_passthrough;
+
+ /* Features that were filtered out because of missing host capabilities */
+ uint32_t filtered_features[FEATURE_WORDS];
+
+ /* Enable PMU CPUID bits. This can't be enabled by default yet because
+ * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
+ * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
+ * capabilities) directly to the guest.
+ */
+ bool enable_pmu;
+
+ /* in order to simplify APIC support, we leave this pointer to the
+ user */
+ struct DeviceState *apic_state;
+ struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
+ Notifier machine_done;
+};
+
+static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
+{
+ return container_of(env, X86CPU, env);
+}
+
+#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
+
+#define ENV_OFFSET offsetof(X86CPU, env)
+
+#ifndef CONFIG_USER_ONLY
+extern struct VMStateDescription vmstate_x86_cpu;
+#endif
+
+/**
+ * x86_cpu_do_interrupt:
+ * @cpu: vCPU the interrupt is to be handled by.
+ */
+void x86_cpu_do_interrupt(CPUState *cpu);
+bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
+int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+
+void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
+
+void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+
+hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
+int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+
+void x86_cpu_exec_enter(CPUState *cpu);
+void x86_cpu_exec_exit(CPUState *cpu);
X86CPU *cpu_x86_init(const char *cpu_model);
X86CPU *cpu_x86_create(const char *cpu_model, Error **errp);
--
1.8.3.1
- [Qemu-devel] [PATCH 02/49] log: do not use CONFIG_USER_ONLY, (continued)
- [Qemu-devel] [PATCH 02/49] log: do not use CONFIG_USER_ONLY, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 01/49] include: move CPU-related definitions out of qemu-common.h, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 04/49] cpu: make cpu-qom.h only include-able from cpu.h, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 05/49] target-alpha: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 03/49] hw: explicitly include qemu-common.h and cpu.h, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 06/49] target-arm: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 10/49] target-m68k: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 07/49] target-cris: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 11/49] target-microblaze: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 09/49] target-lm32: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 08/49] target-i386: make cpu-qom.h not target specific,
Paolo Bonzini <=
- [Qemu-devel] [PATCH 12/49] target-mips: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 13/49] target-ppc: do not use target_ulong in cpu-qom.h, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 15/49] target-s390x: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 18/49] target-tricore: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 16/49] target-sh4: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 14/49] target-ppc: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 25/49] mips: use MIPSCPU instead of CPUMIPSState, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 20/49] target-xtensa: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16
- [Qemu-devel] [PATCH 19/49] target-unicore32: make cpu-qom.h not target specific, Paolo Bonzini, 2016/03/16