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[Qemu-devel] [PATCH v2 04/10] ppc: Create cpu_ppc_set_papr() helper
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v2 04/10] ppc: Create cpu_ppc_set_papr() helper |
Date: |
Wed, 16 Mar 2016 14:13:48 +0100 |
From: Benjamin Herrenschmidt <address@hidden>
And move the code adjusting the MSR mask and calling kvmppc_set_papr()
to it. This allows us to add a few more things such as disabling setting
of MSR:HV and appropriate LPCR bits which will be used when fixing
the exception model.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
---
hw/ppc/spapr.c | 11 ++---------
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 37 ++++++++++++++++++++++++++++++++++++-
3 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 79a70a9c0fc3..cc7431674771 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1612,15 +1612,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr,
PowerPCCPU *cpu,
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, TIMEBASE_FREQ);
- /* PAPR always has exception vectors in RAM not ROM. To ensure this,
- * MSR[IP] should never be set.
- */
- env->msr_mask &= ~(1 << 6);
-
- /* Tell KVM that we're in PAPR mode */
- if (kvm_enabled()) {
- kvmppc_set_papr(cpu);
- }
+ /* Enable PAPR mode in TCG or KVM */
+ cpu_ppc_set_papr(cpu);
if (cpu->max_compat) {
Error *local_err = NULL;
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 9ce301f18922..a7da0d3e95a9 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all (CPUPPCState *env);
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
+void cpu_ppc_set_papr(PowerPCCPU *cpu);
#endif
#endif
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4cb3dd5076c1..aaf8ad79361e 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8380,8 +8380,43 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
}
-#endif /* defined (TARGET_PPC64) */
+#if !defined(CONFIG_USER_ONLY)
+
+void cpu_ppc_set_papr(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+ ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
+
+ /* PAPR always has exception vectors in RAM not ROM. To ensure this,
+ * MSR[IP] should never be set.
+ *
+ * We also disallow setting of MSR_HV
+ */
+ env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
+
+ /* Set emulated LPCR to not send interrupts to hypervisor. Note that
+ * under KVM, the actual HW LPCR will be set differently by KVM itself,
+ * the settings below ensure proper operations with TCG in absence of
+ * a real hypervisor
+ */
+ lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
+ lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
+
+ /* We should be followed by a CPU reset but update the active value
+ * just in case...
+ */
+ env->spr[SPR_LPCR] = lpcr->default_value;
+
+ /* Tell KVM that we're in PAPR mode */
+ if (kvm_enabled()) {
+ kvmppc_set_papr(cpu);
+ }
+}
+
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+#endif /* defined (TARGET_PPC64) */
/*****************************************************************************/
/* Generic CPU instantiation routine */
--
2.1.4
- [Qemu-devel] [PATCH v2 00/10] ppc: preparing pnv landing, Cédric Le Goater, 2016/03/16
- [Qemu-devel] [PATCH v2 02/10] ppc: Add macros to register hypervisor mode SPRs, Cédric Le Goater, 2016/03/16
- [Qemu-devel] [PATCH v2 01/10] ppc: Update SPR definitions, Cédric Le Goater, 2016/03/16
- [Qemu-devel] [PATCH v2 06/10] ppc: Initialize AMOR in PAPR mode, Cédric Le Goater, 2016/03/16
- [Qemu-devel] [PATCH v2 05/10] ppc: Add dummy SPR_IC for POWER8, Cédric Le Goater, 2016/03/16
- [Qemu-devel] [PATCH v2 03/10] ppc: Add a bunch of hypervisor SPRs to Book3s, Cédric Le Goater, 2016/03/16
- [Qemu-devel] [PATCH v2 04/10] ppc: Create cpu_ppc_set_papr() helper,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v2 07/10] ppc: Fix writing to AMR/UAMOR, Cédric Le Goater, 2016/03/16
- [Qemu-devel] [PATCH v2 10/10] ppc: A couple more dummy POWER8 Book4 regs, Cédric Le Goater, 2016/03/16
- [Qemu-devel] [PATCH v2 08/10] ppc: Add POWER8 IAMR register, Cédric Le Goater, 2016/03/16