Re: [Qemu-devel] Request for help with Qemu GDB for big-endian instructions (R4)

[Peter Maydell]

On 16 March 2016 at 10:06, Paul, Kaustav Kumar <address@hidden> wrote:
> The firmware is compiled for Cortex-R4, runs ThreadX OS and is configured to
> use both instructions and data in big-endian (BE32 ?) format.

The Cortex-R4 is an ARMv7 CPU, and so only supports BE8.

> The code is
> compiled with GHS toolchain. I understand that out of the box, GDB will not
> be able to do source code debugging. However, I expected that it’ll at least
> be able to do assembly level debugging. We have another ASIC with Cortex-A9
> configured for BE8, also running ThreadX. And it does work at assembly
> level.

First of all, please retry this with QEMU built from current git master.
A lot of patches went in a few weeks ago to improve our big-endian
support. We may well still have some bugs, but there doesn't seem much
point trying to diagnose problems in the old code...

That said, if your R4 is configured to use big-endian instruction
order (presumably by the CFGIE signal being set high), then you're
probably running into the fact that QEMU does not implement the
(PMSAv7) SCTLR.IE bit which allows big-endian instructions for R profile.

Further questions:
 (1) we don't implement an R4 model at all in QEMU (we do have an R5),
     so are you using some out of tree patches for R4 support or are
     you trying to run the code on an R5 CPU?
 (2) which board model are you using? One in QEMU mainline or an out
     of tree one? What is your QEMU command line?

Regarding gdb, QEMU just provides facilities for reading and writing
memory, so if asking gdb to do a memory dump shows correct data but
disassembly does not, then the problem is at the gdb end (probably
a config switch); you probably need to ask a gdb person about that.

thanks
-- PMM