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[Qemu-devel] [PULL 03/21] target-arm: Fix translation level on early tra
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/21] target-arm: Fix translation level on early translation faults |
Date: |
Wed, 16 Mar 2016 17:18:17 +0000 |
From: Sergey Sorokin <address@hidden>
Qemu reports translation fault on 1st level instead of 0th level in case of
AArch64 address translation if the translation table walk is disabled or
the address is in the gap between the two regions.
Signed-off-by: Sergey Sorokin <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index eaded41..19d5d52 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -7237,7 +7237,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
CPUState *cs = CPU(cpu);
/* Read an LPAE long-descriptor translation table. */
MMUFaultType fault_type = translation_fault;
- uint32_t level = 1;
+ uint32_t level;
uint32_t epd = 0;
int32_t t0sz, t1sz;
uint32_t tg;
@@ -7248,7 +7248,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
target_ulong page_size;
uint32_t attrs;
int32_t stride = 9;
- int32_t va_size = 32;
+ int32_t va_size;
int inputsize;
int32_t tbi = 0;
TCR *tcr = regime_tcr(env, mmu_idx);
@@ -7264,6 +7264,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
* support for those page table walks.
*/
if (arm_el_is_aa64(env, el)) {
+ level = 0;
va_size = 64;
if (el > 1) {
if (mmu_idx != ARMMMUIdx_S2NS) {
@@ -7285,6 +7286,8 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
ttbr1_valid = false;
}
} else {
+ level = 1;
+ va_size = 32;
/* There is no TTBR1 for EL2 */
if (el == 2) {
ttbr1_valid = false;
@@ -7407,27 +7410,26 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
/* For stage 2 translations the starting level is specified by the
* VTCR_EL2.SL0 field (whose interpretation depends on the page size)
*/
- int startlevel = extract32(tcr->raw_tcr, 6, 2);
+ uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
+ uint32_t startlevel;
bool ok;
if (va_size == 32 || stride == 9) {
/* AArch32 or 4KB pages */
- level = 2 - startlevel;
+ startlevel = 2 - sl0;
} else {
/* 16KB or 64KB pages */
- level = 3 - startlevel;
+ startlevel = 3 - sl0;
}
/* Check that the starting level is valid. */
- ok = check_s2_mmu_setup(cpu, va_size == 64, level, inputsize, stride);
+ ok = check_s2_mmu_setup(cpu, va_size == 64, startlevel,
+ inputsize, stride);
if (!ok) {
- /* AArch64 reports these as level 0 faults.
- * AArch32 reports these as level 1 faults.
- */
- level = va_size == 64 ? 0 : 1;
fault_type = translation_fault;
goto do_fault;
}
+ level = startlevel;
}
/* Clear the vaddr bits which aren't part of the within-region address,
--
1.9.1
- [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 16/21] bcm2835_peripherals: enable sdhci pending-insert quirk for raspberry pi, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 15/21] hw/arm: Add palmetto-bmc machine, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 14/21] hw/arm: Add ASPEED AST2400 SoC model, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 03/21] target-arm: Fix translation level on early translation faults,
Peter Maydell <=
- [Qemu-devel] [PULL 09/21] i.MX: Add the CLK_IPG_HIGH clock, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 07/21] i.MX: Rename CCM NOCLK to CLK_NONE for naming consistency., Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 05/21] arm: virt: Move machine class init code to the abstract machine type, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 08/21] i.MX: Remove CCM useless clock computation handling., Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 11/21] i.MX: Add missing descriptions in devices., Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 21/21] sd: Fix "info qtree" on boards with SD cards, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 17/21] bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 19/21] bcm2835_property: implement framebuffer control/configuration properties, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 02/21] target-arm: Implement MRS (banked) and MSR (banked) instructions, Peter Maydell, 2016/03/16
- [Qemu-devel] [PULL 12/21] hw/timer: Add ASPEED timer device model, Peter Maydell, 2016/03/16