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Re: [Qemu-devel] [PATCH v5 00/11] Support for N25Q256/512 and AT25128/25
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v5 00/11] Support for N25Q256/512 and AT25128/256 |
Date: |
Wed, 23 Mar 2016 15:30:39 +0000 |
On 20 March 2016 at 18:28, <address@hidden> wrote:
> From: Marcin Krzeminski <address@hidden>
>
> V5: Changes after review
> - Macrofication of registers values
> - Numonyx is default value in switch for fast read family
> V4:
> - Fixed RNVCR command (needed bytes set to 2 instead of 1)
> - Config registers are configured only for micron flash devices
> - Move config registers initialization to reset_memory function
> - Removed clearing reset_enable flag when chip was selcted by CS signal
> V3:
> - Checkpatch run on patches
> - Renamed function
> V2:
> - Removed support for mx66u51235 and s25fl512s from this series
> - Corrected/implemented dummy cycles
> - rebased to master
Applied to target-arm.next, thanks.
-- PMM
- [Qemu-devel] [PATCH v5 09/11] block: m25p80: Implemented FSR register, (continued)
- [Qemu-devel] [PATCH v5 09/11] block: m25p80: Implemented FSR register, marcin . krzeminski, 2016/03/20
- [Qemu-devel] [PATCH v5 11/11] block: m25p80: at25128a/at25256a models, marcin . krzeminski, 2016/03/20
- [Qemu-devel] [PATCH v5 06/11] block: m25p80: Add configuration registers, marcin . krzeminski, 2016/03/20
- [Qemu-devel] [PATCH v5 07/11] block: m25p80: Dummy cycles for N25Q256/512, marcin . krzeminski, 2016/03/20
- [Qemu-devel] [PATCH v5 04/11] block: m25p80: Extend address mode, marcin . krzeminski, 2016/03/20
- [Qemu-devel] [PATCH v5 08/11] block: m25p80: Fast read and 4bytes commands, marcin . krzeminski, 2016/03/20
- [Qemu-devel] [PATCH v5 05/11] block: m25p80: 4byte address mode, marcin . krzeminski, 2016/03/20
- [Qemu-devel] [PATCH v5 03/11] block: m25p80: Widen flags variable, marcin . krzeminski, 2016/03/20
- Re: [Qemu-devel] [PATCH v5 00/11] Support for N25Q256/512 and AT25128/256,
Peter Maydell <=