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[Qemu-devel] [PULL v2 19/21] hw/mips/cps: enable ITU for multithreading
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL v2 19/21] hw/mips/cps: enable ITU for multithreading processors |
Date: |
Wed, 30 Mar 2016 09:50:00 +0100 |
Make ITU available in the system if CPU supports multithreading
and is part of CPS.
Signed-off-by: Leon Alrae <address@hidden>
---
hw/mips/cps.c | 32 ++++++++++++++++++++++++++++++++
include/hw/mips/cps.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index d46547c..1bafbbb 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -22,6 +22,7 @@
#include "hw/mips/cps.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
+#include "sysemu/kvm.h"
qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
{
@@ -56,6 +57,14 @@ static void main_cpu_reset(void *opaque)
cs->halted = 1;
}
+static bool cpu_mips_itu_supported(CPUMIPSState *env)
+{
+ bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
+ (env->CP0_Config3 & (1 << CP0C3_MT));
+
+ return is_mt && !kvm_enabled();
+}
+
static void mips_cps_realize(DeviceState *dev, Error **errp)
{
MIPSCPSState *s = MIPS_CPS(dev);
@@ -64,6 +73,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
int i;
Error *err = NULL;
target_ulong gcr_base;
+ bool itu_present = false;
for (i = 0; i < s->num_vp; i++) {
cpu = cpu_mips_init(s->cpu_model);
@@ -76,12 +86,34 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
/* Init internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
+ if (cpu_mips_itu_supported(env)) {
+ itu_present = true;
+ /* Attach ITC Tag to the VP */
+ env->itc_tag = mips_itu_get_tag_region(&s->itu);
+ }
qemu_register_reset(main_cpu_reset, cpu);
}
cpu = MIPS_CPU(first_cpu);
env = &cpu->env;
+ /* Inter-Thread Communication Unit */
+ if (itu_present) {
+ object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
+ qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
+
+ object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
+ object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
+ object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ memory_region_add_subregion(&s->container, 0,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
+ }
+
/* Cluster Power Controller */
object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index 88be765..4dbae9c 100644
--- a/include/hw/mips/cps.h
+++ b/include/hw/mips/cps.h
@@ -23,6 +23,7 @@
#include "hw/sysbus.h"
#include "hw/misc/mips_cmgcr.h"
#include "hw/misc/mips_cpc.h"
+#include "hw/misc/mips_itu.h"
#define TYPE_MIPS_CPS "mips-cps"
#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
@@ -37,6 +38,7 @@ typedef struct MIPSCPSState {
MemoryRegion container;
MIPSGCRState gcr;
MIPSCPCState cpc;
+ MIPSITUState itu;
} MIPSCPSState;
qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
--
2.1.0
- [Qemu-devel] [PULL v2 10/21] hw/mips_malta: add CPS to Malta board, (continued)
- [Qemu-devel] [PULL v2 10/21] hw/mips_malta: add CPS to Malta board, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 04/21] hw/mips/cps: create GCR block inside CPS, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 13/21] hw/mips: implement ITC Storage - Control View, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 01/21] hw/mips: implement generic MIPS Coherent Processing System container, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 03/21] hw/mips: add initial Global Config Register support, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 06/21] hw/mips/cps: create CPC block inside CPS, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 09/21] hw/mips_malta: move CPU creation to a separate function, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 16/21] hw/mips: implement ITC Storage - Bypass View, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 12/21] hw/mips: implement ITC Configuration Tags and Storage Cells, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 19/21] hw/mips/cps: enable ITU for multithreading processors,
Leon Alrae <=
- [Qemu-devel] [PULL v2 20/21] target-mips: use CP0_CHECK for gen_m{f|t}hc0, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 15/21] hw/mips: implement ITC Storage - P/V Sync and Try Views, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader(), Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 08/21] hw/mips_malta: remove redundant irq and clock init, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 18/21] target-mips: make ITC Configuration Tags accessible to the CPU, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 21/21] target-mips: add MAAR, MAARI register, Leon Alrae, 2016/03/30
- Re: [Qemu-devel] [PULL v2 00/21] target-mips queue for 2.6, Peter Maydell, 2016/03/30