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[Qemu-devel] [PATCH 5/8] target/ppc: Optimize emulation of vclzd instruc
From: |
Stefan Brankovic |
Subject: |
[Qemu-devel] [PATCH 5/8] target/ppc: Optimize emulation of vclzd instruction |
Date: |
Thu, 6 Jun 2019 12:15:27 +0200 |
Optimize Altivec instruction vclzd (Vector Count Leading Zeros Doubleword).
This instruction counts the number of leading zeros of each doubleword element
in source register and places result in the appropriate doubleword element of
destination register.
Using tcg-s count leading zeros instruction two times(once for each
doubleword element of source register vB) and placing result in
appropriate doubleword element of destination register vD.
Signed-off-by: Stefan Brankovic <address@hidden>
---
target/ppc/translate/vmx-impl.inc.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate/vmx-impl.inc.c
b/target/ppc/translate/vmx-impl.inc.c
index 010f337..1c34908 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -877,6 +877,32 @@ static void trans_vgbbd(DisasContext *ctx)
tcg_temp_free_i64(result2);
}
+/*
+ * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
+ *
+ * Counting the number of leading zero bits of each doubleword element in
source
+ * register and placing result in appropriate doubleword element of destination
+ * register.
+ */
+static void trans_vclzd(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i64 avr = tcg_temp_new_i64();
+
+ /* high doubleword */
+ get_avr64(avr, VB, true);
+ tcg_gen_clzi_i64(avr, avr, 64);
+ set_avr64(VT, avr, true);
+
+ /* low doubleword */
+ get_avr64(avr, VB, false);
+ tcg_gen_clzi_i64(avr, avr, 64);
+ set_avr64(VT, avr, false);
+
+ tcg_temp_free_i64(avr);
+}
+
GEN_VXFORM(vmuloub, 4, 0);
GEN_VXFORM(vmulouh, 4, 1);
GEN_VXFORM(vmulouw, 4, 2);
@@ -1388,7 +1414,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
GEN_VXFORM_NOA(vclzb, 1, 28)
GEN_VXFORM_NOA(vclzh, 1, 29)
GEN_VXFORM_NOA(vclzw, 1, 30)
-GEN_VXFORM_NOA(vclzd, 1, 31)
+GEN_VXFORM_TRANS(vclzd, 1, 31)
GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
--
2.7.4
- [Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions, (continued)
- [Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions, Stefan Brankovic, 2019/06/06
- [Qemu-devel] [PATCH 4/8] target/ppc: Optimize emulation of vgbbd instruction, Stefan Brankovic, 2019/06/06
- [Qemu-devel] [PATCH 7/8] target/ppc: Optimize emulation of vclzh and vclzb instructions, Stefan Brankovic, 2019/06/06
- [Qemu-devel] [PATCH 3/8] target/ppc: Optimize emulation of vpkpx instruction, Stefan Brankovic, 2019/06/06
- [Qemu-devel] [PATCH 5/8] target/ppc: Optimize emulation of vclzd instruction,
Stefan Brankovic <=
- [Qemu-devel] [PATCH 8/8] target/ppc: Refactor emulation of vmrgew and vmrgow instructions, Stefan Brankovic, 2019/06/06
- [Qemu-devel] [PATCH 6/8] target/ppc: Optimize emulation of vclzw instruction, Stefan Brankovic, 2019/06/06
- Re: [Qemu-devel] [PATCH 0/8] Optimize emulation of ten Altivec instructions: lvsl,, Richard Henderson, 2019/06/06