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[Qemu-devel] [PULL 00/48] target-arm queue
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 00/48] target-arm queue |
Date: |
Thu, 13 Jun 2019 13:13:45 +0100 |
Arm queue; the bulk of this is the VFP decodetree conversion...
thanks
-- PMM
The following changes since commit 4747524f9f243ca5ff1f146d37e423c00e923ee1:
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2019-06-12' into
staging (2019-06-13 11:58:00 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20190613
for you to fetch changes up to 07e4c7f769120c9a5bd6a26c2dc1421f2f838d80:
target/arm: Fix short-vector increment behaviour (2019-06-13 12:57:37 +0100)
----------------------------------------------------------------
target-arm queue:
* convert aarch32 VFP decoder to decodetree
(includes tightening up decode in a few places)
* fix minor bugs in VFP short-vector handling
* hw/core/bus.c: Only the main system bus can have no parent
* smmuv3: Fix decoding of ID register range
* Implement NSACR gating of floating point
* Use tcg_gen_gvec_bitsel
* Vectorize USHL and SSHL
----------------------------------------------------------------
Peter Maydell (44):
target/arm: Implement NSACR gating of floating point
hw/arm/smmuv3: Fix decoding of ID register range
hw/core/bus.c: Only the main system bus can have no parent
target/arm: Add stubs for AArch32 VFP decodetree
target/arm: Factor out VFP access checking code
target/arm: Fix Cortex-R5F MVFR values
target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max
target/arm: Convert the VSEL instructions to decodetree
target/arm: Convert VMINNM, VMAXNM to decodetree
target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree
target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c
target/arm: Add helpers for VFP register loads and stores
target/arm: Convert "double-precision" register moves to decodetree
target/arm: Convert "single-precision" register moves to decodetree
target/arm: Convert VFP two-register transfer insns to decodetree
target/arm: Convert VFP VLDR and VSTR to decodetree
target/arm: Convert the VFP load/store multiple insns to decodetree
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d
target/arm: Convert VFP VMLA to decodetree
target/arm: Convert VFP VMLS to decodetree
target/arm: Convert VFP VNMLS to decodetree
target/arm: Convert VFP VNMLA to decodetree
target/arm: Convert VMUL to decodetree
target/arm: Convert VNMUL to decodetree
target/arm: Convert VADD to decodetree
target/arm: Convert VSUB to decodetree
target/arm: Convert VDIV to decodetree
target/arm: Convert VFP fused multiply-add insns to decodetree
target/arm: Convert VMOV (imm) to decodetree
target/arm: Convert VABS to decodetree
target/arm: Convert VNEG to decodetree
target/arm: Convert VSQRT to decodetree
target/arm: Convert VMOV (register) to decodetree
target/arm: Convert VFP comparison insns to decodetree
target/arm: Convert the VCVT-from-f16 insns to decodetree
target/arm: Convert the VCVT-to-f16 insns to decodetree
target/arm: Convert VFP round insns to decodetree
target/arm: Convert double-single precision conversion insns to decodetree
target/arm: Convert integer-to-float insns to decodetree
target/arm: Convert VJCVT to decodetree
target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree
target/arm: Convert float-to-integer VCVT insns to decodetree
target/arm: Fix short-vector increment behaviour
Richard Henderson (4):
target/arm: Vectorize USHL and SSHL
target/arm: Use tcg_gen_gvec_bitsel
target/arm: Fix output of PAuth Auth
decodetree: Fix comparison of Field
target/arm/Makefile.objs | 13 +
tests/tcg/aarch64/Makefile.target | 2 +-
target/arm/cpu.h | 11 +
target/arm/helper.h | 11 +-
target/arm/translate-a64.h | 2 +
target/arm/translate.h | 9 +-
hw/arm/smmuv3.c | 2 +-
hw/core/bus.c | 21 +-
target/arm/cpu.c | 6 +
target/arm/helper.c | 75 +-
target/arm/neon_helper.c | 33 -
target/arm/pauth_helper.c | 4 +-
target/arm/translate-a64.c | 33 +-
target/arm/translate-vfp.inc.c | 2672 +++++++++++++++++++++++++++++++++++++
target/arm/translate.c | 1881 +++++---------------------
target/arm/vec_helper.c | 88 ++
tests/tcg/aarch64/pauth-2.c | 61 +
scripts/decodetree.py | 2 +-
target/arm/vfp-uncond.decode | 63 +
target/arm/vfp.decode | 242 ++++
20 files changed, 3593 insertions(+), 1638 deletions(-)
create mode 100644 target/arm/translate-vfp.inc.c
create mode 100644 tests/tcg/aarch64/pauth-2.c
create mode 100644 target/arm/vfp-uncond.decode
create mode 100644 target/arm/vfp.decode
- [Qemu-devel] [PULL 00/48] target-arm queue,
Peter Maydell <=
- [Qemu-devel] [PULL 01/48] target/arm: Vectorize USHL and SSHL, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 02/48] target/arm: Use tcg_gen_gvec_bitsel, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 06/48] target/arm: Fix output of PAuth Auth, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 07/48] decodetree: Fix comparison of Field, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 12/48] target/arm: Convert the VSEL instructions to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 11/48] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 08/48] target/arm: Add stubs for AArch32 VFP decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 10/48] target/arm: Fix Cortex-R5F MVFR values, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 20/48] target/arm: Convert VFP two-register transfer insns to decodetree, Peter Maydell, 2019/06/13