[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 43/48] target/arm: Convert double-single precision co
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 43/48] target/arm: Convert double-single precision conversion insns to decodetree |
Date: |
Thu, 13 Jun 2019 13:14:28 +0100 |
Convert the VCVT double/single precision conversion insns to decodetree.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/translate-vfp.inc.c | 48 ++++++++++++++++++++++++++++++++++
target/arm/translate.c | 13 +--------
target/arm/vfp.decode | 6 +++++
3 files changed, 55 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index e94a8f2f0c5..c50093776b6 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -2320,3 +2320,51 @@ static bool trans_VRINTX_dp(DisasContext *s,
arg_VRINTX_dp *a)
tcg_temp_free_i64(tmp);
return true;
}
+
+static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
+{
+ TCGv_i64 vd;
+ TCGv_i32 vm;
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vm = tcg_temp_new_i32();
+ vd = tcg_temp_new_i64();
+ neon_load_reg32(vm, a->vm);
+ gen_helper_vfp_fcvtds(vd, vm, cpu_env);
+ neon_store_reg64(vd, a->vd);
+ tcg_temp_free_i32(vm);
+ tcg_temp_free_i64(vd);
+ return true;
+}
+
+static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
+{
+ TCGv_i64 vm;
+ TCGv_i32 vd;
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vd = tcg_temp_new_i32();
+ vm = tcg_temp_new_i64();
+ neon_load_reg64(vm, a->vm);
+ gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
+ neon_store_reg32(vd, a->vd);
+ tcg_temp_free_i32(vd);
+ tcg_temp_free_i64(vm);
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0c855069d85..40e52c3b700 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
return 1;
case 15:
switch (rn) {
- case 0 ... 14:
+ case 0 ... 15:
/* Already handled by decodetree */
return 1;
default:
@@ -3063,10 +3063,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
if (op == 15) {
/* rn is opcode, encoded as per VFP_SREG_N. */
switch (rn) {
- case 0x0f: /* vcvt double<->single */
- rd_is_dp = !dp;
- break;
-
case 0x10: /* vcvt.fxx.u32 */
case 0x11: /* vcvt.fxx.s32 */
rm_is_dp = false;
@@ -3185,13 +3181,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
switch (op) {
case 15: /* extension space */
switch (rn) {
- case 15: /* single<->double conversion */
- if (dp) {
- gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
- } else {
- gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
- }
- break;
case 16: /* fuito */
gen_vfp_uito(dp, 0);
break;
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 9942d2ae7ad..56b8b4e6046 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -208,3 +208,9 @@ VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \
vd=%vd_sp vm=%vm_sp
VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \
vd=%vd_dp vm=%vm_dp
+
+# VCVT between single and double: Vm precision depends on size; Vd is its
reverse
+VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \
+ vd=%vd_dp vm=%vm_sp
+VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \
+ vd=%vd_sp vm=%vm_dp
--
2.20.1
- [Qemu-devel] [PULL 04/48] hw/arm/smmuv3: Fix decoding of ID register range, (continued)
- [Qemu-devel] [PULL 04/48] hw/arm/smmuv3: Fix decoding of ID register range, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 03/48] target/arm: Implement NSACR gating of floating point, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 18/48] target/arm: Convert "double-precision" register moves to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 28/48] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 30/48] target/arm: Convert VADD to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 27/48] target/arm: Convert VFP VNMLA to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 09/48] target/arm: Factor out VFP access checking code, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 25/48] target/arm: Convert VFP VMLS to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 31/48] target/arm: Convert VSUB to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 43/48] target/arm: Convert double-single precision conversion insns to decodetree,
Peter Maydell <=
- [Qemu-devel] [PULL 42/48] target/arm: Convert VFP round insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 23/48] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 45/48] target/arm: Convert VJCVT to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 47/48] target/arm: Convert float-to-integer VCVT insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 32/48] target/arm: Convert VDIV to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 35/48] target/arm: Convert VABS to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 44/48] target/arm: Convert integer-to-float insns to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 29/48] target/arm: Convert VNMUL to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 14/48] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree, Peter Maydell, 2019/06/13
- [Qemu-devel] [PULL 24/48] target/arm: Convert VFP VMLA to decodetree, Peter Maydell, 2019/06/13