Re: [Qemu-devel] [PULL 00/48] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PULL 00/48] target-arm queue
Type: series
Message-id: address@hidden

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
4a4f476 target/arm: Fix short-vector increment behaviour
f97969f target/arm: Convert float-to-integer VCVT insns to decodetree
06691bd target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree
8eccbb7 target/arm: Convert VJCVT to decodetree
b0dd5ef target/arm: Convert integer-to-float insns to decodetree
c0b43d7 target/arm: Convert double-single precision conversion insns to 
decodetree
bdaf9a7 target/arm: Convert VFP round insns to decodetree
4606cac target/arm: Convert the VCVT-to-f16 insns to decodetree
db43590 target/arm: Convert the VCVT-from-f16 insns to decodetree
15014fa target/arm: Convert VFP comparison insns to decodetree
72b8973 target/arm: Convert VMOV (register) to decodetree
739f1ab target/arm: Convert VSQRT to decodetree
6a56019 target/arm: Convert VNEG to decodetree
379e393 target/arm: Convert VABS to decodetree
74fc301 target/arm: Convert VMOV (imm) to decodetree
1f17937 target/arm: Convert VFP fused multiply-add insns to decodetree
70823b7 target/arm: Convert VDIV to decodetree
6520422 target/arm: Convert VSUB to decodetree
9269b51a target/arm: Convert VADD to decodetree
acedef4 target/arm: Convert VNMUL to decodetree
cf8b56a target/arm: Convert VMUL to decodetree
b7a9e2b target/arm: Convert VFP VNMLA to decodetree
f0fc7fd target/arm: Convert VFP VNMLS to decodetree
e4a623d target/arm: Convert VFP VMLS to decodetree
c5b5ba8 target/arm: Convert VFP VMLA to decodetree
0da58fc target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d
4f1d141 target/arm: Convert the VFP load/store multiple insns to decodetree
f4b6b93 target/arm: Convert VFP VLDR and VSTR to decodetree
78e28fd target/arm: Convert VFP two-register transfer insns to decodetree
ba4a37a target/arm: Convert "single-precision" register moves to decodetree
aeab2cf target/arm: Convert "double-precision" register moves to decodetree
53b5090 target/arm: Add helpers for VFP register loads and stores
ab9287c target/arm: Move the VFP trans_* functions to translate-vfp.inc.c
e06d146 target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree
bdec29d target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree
7962823 target/arm: Convert VMINNM, VMAXNM to decodetree
2e9703a target/arm: Convert the VSEL instructions to decodetree
f701974 target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max
45eaaf7 target/arm: Fix Cortex-R5F MVFR values
ec42b7e target/arm: Factor out VFP access checking code
733acd8 target/arm: Add stubs for AArch32 VFP decodetree
c2126a5 decodetree: Fix comparison of Field
67fada0 target/arm: Fix output of PAuth Auth
8a523c7 hw/core/bus.c: Only the main system bus can have no parent
c6fec21 hw/arm/smmuv3: Fix decoding of ID register range
822c46e target/arm: Implement NSACR gating of floating point
ee350d4 target/arm: Use tcg_gen_gvec_bitsel
e8b1a26 target/arm: Vectorize USHL and SSHL

=== OUTPUT BEGIN ===
1/48 Checking commit e8b1a2672c18 (target/arm: Vectorize USHL and SSHL)
ERROR: trailing statements should be on next line
#163: FILE: target/arm/translate.c:5377:
+            case 2: gen_ushl_i32(var, var, shift); break;

ERROR: trailing statements should be on next line
#170: FILE: target/arm/translate.c:5383:
+            case 2: gen_sshl_i32(var, var, shift); break;

total: 2 errors, 0 warnings, 570 lines checked

Patch 1/48 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

2/48 Checking commit ee350d4faf84 (target/arm: Use tcg_gen_gvec_bitsel)
3/48 Checking commit 822c46ed48fa (target/arm: Implement NSACR gating of 
floating point)
4/48 Checking commit c6fec217c968 (hw/arm/smmuv3: Fix decoding of ID register 
range)
5/48 Checking commit 8a523c7ea9f1 (hw/core/bus.c: Only the main system bus can 
have no parent)
6/48 Checking commit 67fada0513da (target/arm: Fix output of PAuth Auth)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#49: 
new file mode 100644

total: 0 errors, 1 warnings, 80 lines checked

Patch 6/48 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/48 Checking commit c2126a541532 (decodetree: Fix comparison of Field)
8/48 Checking commit 733acd830289 (target/arm: Add stubs for AArch32 VFP 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51: 
new file mode 100644

total: 0 errors, 1 warnings, 136 lines checked

Patch 8/48 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/48 Checking commit ec42b7e736a9 (target/arm: Factor out VFP access checking 
code)
10/48 Checking commit 45eaaf72def8 (target/arm: Fix Cortex-R5F MVFR values)
11/48 Checking commit f701974e16a8 (target/arm: Explicitly enable VFP 
short-vectors for aarch32 -cpu max)
12/48 Checking commit 2e9703a17c6d (target/arm: Convert the VSEL instructions 
to decodetree)
13/48 Checking commit 7962823a9836 (target/arm: Convert VMINNM, VMAXNM to 
decodetree)
14/48 Checking commit bdec29d22fff (target/arm: Convert 
VRINTA/VRINTN/VRINTP/VRINTM to decodetree)
15/48 Checking commit e06d146dce89 (target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM 
to decodetree)
16/48 Checking commit ab9287cd4cc4 (target/arm: Move the VFP trans_* functions 
to translate-vfp.inc.c)
17/48 Checking commit 53b509051833 (target/arm: Add helpers for VFP register 
loads and stores)
18/48 Checking commit aeab2cfe1314 (target/arm: Convert "double-precision" 
register moves to decodetree)
19/48 Checking commit ba4a37af9327 (target/arm: Convert "single-precision" 
register moves to decodetree)
20/48 Checking commit 78e28fdae108 (target/arm: Convert VFP two-register 
transfer insns to decodetree)
21/48 Checking commit f4b6b933a7d2 (target/arm: Convert VFP VLDR and VSTR to 
decodetree)
22/48 Checking commit 4f1d14147730 (target/arm: Convert the VFP load/store 
multiple insns to decodetree)
23/48 Checking commit 0da58fcf8bee (target/arm: Remove VLDR/VSTR/VLDM/VSTM use 
of cpu_F0s and cpu_F0d)
24/48 Checking commit c5b5ba8bd9df (target/arm: Convert VFP VMLA to decodetree)
25/48 Checking commit e4a623dd7ac9 (target/arm: Convert VFP VMLS to decodetree)
26/48 Checking commit f0fc7fd8ee00 (target/arm: Convert VFP VNMLS to decodetree)
27/48 Checking commit b7a9e2bead95 (target/arm: Convert VFP VNMLA to decodetree)
28/48 Checking commit cf8b56a6d150 (target/arm: Convert VMUL to decodetree)
29/48 Checking commit acedef48ad85 (target/arm: Convert VNMUL to decodetree)
30/48 Checking commit 9269b51a4486 (target/arm: Convert VADD to decodetree)
31/48 Checking commit 65204222ea0b (target/arm: Convert VSUB to decodetree)
32/48 Checking commit 70823b7966b6 (target/arm: Convert VDIV to decodetree)
33/48 Checking commit 1f179372cb73 (target/arm: Convert VFP fused multiply-add 
insns to decodetree)
34/48 Checking commit 74fc301b06a2 (target/arm: Convert VMOV (imm) to 
decodetree)
35/48 Checking commit 379e393ab467 (target/arm: Convert VABS to decodetree)
36/48 Checking commit 6a5601909505 (target/arm: Convert VNEG to decodetree)
37/48 Checking commit 739f1abe9682 (target/arm: Convert VSQRT to decodetree)
38/48 Checking commit 72b8973e2922 (target/arm: Convert VMOV (register) to 
decodetree)
39/48 Checking commit 15014fa30c1d (target/arm: Convert VFP comparison insns to 
decodetree)
40/48 Checking commit db43590b700c (target/arm: Convert the VCVT-from-f16 insns 
to decodetree)
41/48 Checking commit 4606cacde3d7 (target/arm: Convert the VCVT-to-f16 insns 
to decodetree)
42/48 Checking commit bdaf9a75455a (target/arm: Convert VFP round insns to 
decodetree)
43/48 Checking commit c0b43d76bddd (target/arm: Convert double-single precision 
conversion insns to decodetree)
44/48 Checking commit b0dd5ef0ef08 (target/arm: Convert integer-to-float insns 
to decodetree)
45/48 Checking commit 8eccbb79c8bf (target/arm: Convert VJCVT to decodetree)
46/48 Checking commit 06691bdf83e9 (target/arm: Convert VCVT fp/fixed-point 
conversion insns to decodetree)
47/48 Checking commit f97969fa5c8c (target/arm: Convert float-to-integer VCVT 
insns to decodetree)
48/48 Checking commit 4a4f47699624 (target/arm: Fix short-vector increment 
behaviour)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to address@hidden