[Qemu-devel] [PATCH 0/6] target/m68k: Overhaul of MOVEC instruction to support exception/MSP

[Lucien Murray-Pitts]

The 68000 does not support the MOVEC instruction, it was added with the 68010.
A new 68010 CPU class was created, and the MOVEC instruction moved to that 
class.

Futher on the 68010, 68060 and CPU32 the ISP doesnt exist.
These CPUs only have SSP/USP.
(NOTE: ColdFire has a different MOVEC helper, this hasnt been touched.)

Unsupported contrl registers (CR) generate a cpu abort, this has been fixed to
correctly generate an ILLEGAL INSTRUCTION exception.

On supporting CPUs the SR register also implements a single bit,  the "M"
(master-mode) bit that determines which of the ISP/MSP is active at the time.
A fix was enetered to support this behavior, with an MSP feature being greated.


Brief overview;
 - Added "CPU class" m68k_feature to each CPU init
   so MOVEC can detect wrong CR (Control Register) access
 - Added cascaded "inheritance" of m68k_features by calling m680xx_cpu_initfn()
   of previous CPU so that 68060 inherits 68040, and so on
 - Added comments above m680xx_cpu_initfn to identify additional supported
   features for that CPU class
 - Added more detailed comments, including CPU classes supported,
   to enum m68k_features
 - Added more detailed comments to each case of m68k_move_to/from helpers
   to list the supported CPUs for that CR
 - Added CPU class detection for each CR type, exits switch if unsupported
 - Added ILLEGAL INSTRUCITON exception condition when the helper fails to
   decode the CR
 - Moved abort only to handle unimplemented control registers,
   all other unknown CR will cause ILLEGAL instruciton
 - Fixed m68k_switch_sp so it switches only if MSP feature is implemented
 - Changed the MOVEC instruction in translate to be 68010 not 68000
 - Added missing BUSCR/PCR CR defines, and decodes for helpers for the 68060

Long overview;

MOVEC EXCEPTIONS
===============================================================================
Because the MOVEC MSP support results in an illegal instruction exception
if the wrong Control Register is accessed then it was necessary to
know the CPU class in the MOVEC instruction (or a less wider method
would be to only check for MOVEC support).

A broader approach was taken to allow any unsupported CR to generate
exceptions.

To do this a sizable overhaul of the CPU initialize funcitons was needed
to add a feature showing the CPU class.

So in the CPU classes the m680XX_cpu_initfn functions have been rearranged
to cascade starting from the base 68000, so that the 68010 then inherits
from this, and so on until the 68060.

Because each cpu class inherits the previous CPU class, then for example
the 68020 also has the feature 68010, and 68000 and so on upto the 68060.

To do this the patch adds classes for each CPU family 680[012346] so that
illegal access to specific control registers can be checked.

The helpers m68k_movec_to, and m68k_movec_from have been updated to support
the exception ILLEGAL INSTRUCTION for all control registers that
are illegal per CPU class, and for any unkown control register.

All other cases will result in an ILLEGAL INSTRUCTION exception as per the
manual. (rather than the abort it used to trigger)


EXTENDED SUPPORT FOR MISSING CONTROL REGISTERS
===============================================================================
Added defines for BUS, and Processor Configuration Register (PCR) for MC68060,
and case statements in the helper for the missing Cache Address Register (CAAR),
and the new BUS, and PCR which results in a cpu abort (unimplemented error)
which doesnt change the behavior for these registers.


SR "M" bit
===============================================================================
The stack swapper helper was fixed to correctly check if the CPU has the MSP,
otherwise defaulting to the ISP always.


COMMENTS
===============================================================================
Additional comments added to the features set to claify
exactly what differentiates each cpu class.  (m68k_features)

Added some more detailed comments to each cpu initialization function
to make it clear the instructions added/changed for that CPU to make
future debugging easier, and the reason for the feature flags more clear.

These comments could go deeper into explaining supported/ehnaced modes,
but this wasnt done in this patch.

There are comments in the existing code referring to the EC/L/and-so-on
classes, however no code has been implemented to handle these specific
varitations of each CPU class, and so no m68k_feature was mde to
distinguish them that way.



Notes:
    Splitting of original patch for clarity as requested by Laurent

    Patch: 20190609164349.GA60211@localhost.localdomain
    ([PATCH v2] Incorrect Stack Pointer shadow register support on some m68k 
CPUs)
      v1->v2
        - Submitted previous patch to fix existing non-compliant comment style 
        - Added a comment about sp in CPUM68KState structure
        - updated movec in the same patch to issue exception
        - Reworked code in m68k_movec_from()/m68k_movec_to() because 
          as they trigger a cpu_abort() with unknown code, 
        - Above rework then required some additions for CPU class and so on.
        - Maybe this is becoming more of an RFC? / should be split for the 
rework?

Based-on: 20190606234125.GA4830@localhost.localdomain
([PATCH v2] m68k comments break patch submission due to being incorrectly 
formatted)



Lucien Murray-Pitts (6):
  m68k cpu instantiation comments improvements
  Cascade m68k_features by m680xx_cpu_initfn() to improve readability
  Improved comments on m68k_move_to/from helpers
  Add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to
    m68k_move_to/from
  MOVEC insn. doesnt generate exception if wrong CR is accessed
  Added MSP detection support for stack pointer swap helpers

 target/m68k/cpu.c       | 109 ++++++++++++++----
 target/m68k/cpu.h       |  56 ++++++---
 target/m68k/helper.c    | 246 +++++++++++++++++++++++++++++++---------
 target/m68k/translate.c |   2 +-
 4 files changed, 320 insertions(+), 93 deletions(-)

-- 
2.21.0