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[Qemu-devel] [PATCH v6 07/16] tcg/ppc: Add support for vector add/subtra
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v6 07/16] tcg/ppc: Add support for vector add/subtract |
Date: |
Sat, 29 Jun 2019 15:00:08 +0200 |
Add support for vector add/subtract using Altivec instructions:
VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
tcg/ppc/tcg-target.inc.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 9c5630dc8a..c31694cc78 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,6 +474,14 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VADDUBM VX4(0)
+#define VADDUHM VX4(64)
+#define VADDUWM VX4(128)
+
+#define VSUBUBM VX4(1024)
+#define VSUBUHM VX4(1088)
+#define VSUBUWM VX4(1152)
+
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
@@ -2833,6 +2841,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_andc_vec:
case INDEX_op_not_vec:
return 1;
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
case INDEX_op_smax_vec:
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
@@ -2933,6 +2943,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
static const uint32_t
+ add_op[4] = { VADDUBM, VADDUHM, VADDUWM, 0 },
+ sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, 0 },
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
@@ -2956,6 +2968,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
return;
+ case INDEX_op_add_vec:
+ insn = add_op[vece];
+ break;
+ case INDEX_op_sub_vec:
+ insn = sub_op[vece];
+ break;
case INDEX_op_smin_vec:
insn = smin_op[vece];
break;
@@ -3254,6 +3272,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
return (TCG_TARGET_REG_BITS == 64 ? &S_S
: TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
--
2.17.1
- [Qemu-devel] [PATCH v6 00/16] tcg/ppc: Add vector opcodes, Richard Henderson, 2019/06/29
- [Qemu-devel] [PATCH v6 13/16] tcg/ppc: Enable Altivec detection, Richard Henderson, 2019/06/29
- [Qemu-devel] [PATCH v6 02/16] tcg/ppc: Introduce macro VX4(), Richard Henderson, 2019/06/29
- [Qemu-devel] [PATCH v6 07/16] tcg/ppc: Add support for vector add/subtract,
Richard Henderson <=
- [Qemu-devel] [PATCH v6 14/16] tcg/ppc: Update vector support to v2.06, Richard Henderson, 2019/06/29
- [Qemu-devel] [PATCH v6 11/16] tcg/ppc: Support vector multiply, Richard Henderson, 2019/06/29
- [Qemu-devel] [PATCH v6 09/16] tcg/ppc: Prepare case for vector multiply, Richard Henderson, 2019/06/29
- [Qemu-devel] [PATCH v6 06/16] tcg/ppc: Add support for vector maximum/minimum, Richard Henderson, 2019/06/29
- [Qemu-devel] [PATCH v6 16/16] tcg/ppc: Update vector support to v3.00, Richard Henderson, 2019/06/29
- [Qemu-devel] [PATCH v6 04/16] tcg/ppc: Enable tcg backend vector compilation, Richard Henderson, 2019/06/29