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[Qemu-devel] [PATCH] tcg: Fix expansion of INDEX_op_not_vec
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH] tcg: Fix expansion of INDEX_op_not_vec |
Date: |
Sat, 29 Jun 2019 15:48:38 +0200 |
This operation can always be emitted, even if we need to
fall back to xor. Adjust the assertions to match.
Signed-off-by: Richard Henderson <address@hidden>
---
While expanding the AA64 vector ORC, Altivec needs a bare NOT operation.
This failure does not appear for aa64 or power8 hosts because we have a
native vector orc and so do not go down this path. It also does not
appear for x86_64 because we don't have a native vector not, and so go
down a different path to expand not via xor with -1.
r~
---
tcg/tcg-op-vec.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index c8fdc24f56..6714991bf4 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -90,6 +90,9 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list,
case INDEX_op_bitsel_vec:
/* These opcodes are mandatory and should not be listed. */
g_assert_not_reached();
+ case INDEX_op_not_vec:
+ /* These opcodes have generic expansions using the above. */
+ g_assert_not_reached();
default:
break;
}
@@ -438,11 +441,14 @@ static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a,
TCGOpcode opc)
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
{
+ const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
+
if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) {
TCGv_vec t = tcg_const_ones_vec_matching(r);
tcg_gen_xor_vec(0, r, a, t);
tcg_temp_free_vec(t);
}
+ tcg_swap_vecop_list(hold_list);
}
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
--
2.17.1
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