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[Qemu-devel] [PATCH 05/10] ppc/xive: Implement TM_PULL_OS_CTX special co
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH 05/10] ppc/xive: Implement TM_PULL_OS_CTX special command |
Date: |
Sun, 30 Jun 2019 22:45:56 +0200 |
When a vCPU is not dispatched anymore on a HW thread, the Hypervisor
(KVM) invalidates the OS interrupt context of a vCPU with this special
command. It returns the OS CAM line value and resets the VO bit.
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/intc/xive.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index cf77bdb7d34a..592c0b70f197 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -334,6 +334,17 @@ static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr
offset,
xive_tctx_notify(tctx, TM_QW1_OS);
}
+static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
+ unsigned size)
+{
+ uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
+ uint32_t qw1w2;
+
+ qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0);
+ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+ return qw1w2;
+}
+
/*
* Define a mapping of "special" operations depending on the TIMA page
* offset and the size of the operation.
@@ -360,6 +371,8 @@ static const XiveTmOp xive_tm_operations[] = {
/* MMIOs above 2K : special operations with side effects */
{ XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg },
{ XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL
},
+ { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx },
+ { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg },
{ XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx },
{ XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx },
@@ -403,7 +416,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset,
uint64_t value,
if (offset & 0x800) {
xto = xive_tm_find_op(offset, size, true);
if (!xto) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA"
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA
"
"@%"HWADDR_PRIx"\n", offset);
} else {
xto->write_handler(tctx, offset, value, size);
--
2.21.0
- [Qemu-devel] [PATCH 00/10] ppc/pnv: add XIVE support for KVM guests, Cédric Le Goater, 2019/06/30
- [Qemu-devel] [PATCH 01/10] ppc/xive: Force the Physical CAM line value to group mode, Cédric Le Goater, 2019/06/30
- [Qemu-devel] [PATCH 02/10] ppc/xive: Make the PIPR register readonly, Cédric Le Goater, 2019/06/30
- [Qemu-devel] [PATCH 03/10] ppc/pnv: Rework cache watch model of PnvXIVE, Cédric Le Goater, 2019/06/30
- [Qemu-devel] [PATCH 04/10] ppc/xive: Fix TM_PULL_POOL_CTX special operation, Cédric Le Goater, 2019/06/30
- [Qemu-devel] [PATCH 05/10] ppc/xive: Implement TM_PULL_OS_CTX special command,
Cédric Le Goater <=
- [Qemu-devel] [PATCH 06/10] ppc/xive: Provide escalation support, Cédric Le Goater, 2019/06/30
- [Qemu-devel] [PATCH 07/10] ppc/xive: Improve 'info pic' support, Cédric Le Goater, 2019/06/30
- [Qemu-devel] [PATCH 10/10] ppc/pnv: Dump the XIVE NVT table, Cédric Le Goater, 2019/06/30
- [Qemu-devel] [PATCH 08/10] ppc/xive: Extend XiveTCTX with an router object pointer, Cédric Le Goater, 2019/06/30
- [Qemu-devel] [PATCH 09/10] ppc/xive: Synthesize interrupt from the saved IPB in the NVT, Cédric Le Goater, 2019/06/30