Re: [Qemu-devel] [PATCH v2 16/21] aspeed/smc: add DMA calibration settings

[Peter Maydell]

On Tue, 18 Jun 2019 at 17:55, Cédric Le Goater <address@hidden> wrote:
>
> When doing calibration, the SPI clock rate in the CE0 Control Register
> and the read delay cycles in the Read Timing Compensation Register are
> set using bit[11:4] of the DMA Control Register.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
> Acked-by: Joel Stanley <address@hidden>
> ---
>  hw/ssi/aspeed_smc.c | 64 ++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 63 insertions(+), 1 deletion(-)

Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM