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[Qemu-devel] [PATCH v3 21/27] target/arm: Declare some M-profile functio
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v3 21/27] target/arm: Declare some M-profile functions publicly |
Date: |
Mon, 1 Jul 2019 15:25:10 +0200 |
In the next commit we will split the M-profile functions from this
file. Some function will be called out of helper.c. Declare them in
the "internals.h" header.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
v3: Was v7-only, add v8
---
target/arm/helper.c | 38 ++------------------------------------
target/arm/internals.h | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+), 36 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 515a82af57..4e59ae4d96 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -41,21 +41,6 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
hwaddr *phys_ptr, MemTxAttrs *txattrs, int
*prot,
target_ulong *page_size_ptr,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
-
-/* Security attributes for an address, as returned by v8m_security_lookup. */
-typedef struct V8M_SAttributes {
- bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
- bool ns;
- bool nsc;
- uint8_t sregion;
- bool srvalid;
- uint8_t iregion;
- bool irvalid;
-} V8M_SAttributes;
-
-static void v8m_security_lookup(CPUARMState *env, uint32_t address,
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
- V8M_SAttributes *sattrs);
#endif
static void switch_mode(CPUARMState *env, int mode);
@@ -7735,25 +7720,6 @@ void arm_log_exception(int idx)
}
}
-/*
- * Return true if the v7M CPACR permits access to the FPU for the specified
- * security state and privilege level.
- */
-static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv)
-{
- switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
- case 0:
- case 2: /* UNPREDICTABLE: we treat like 0 */
- return false;
- case 1:
- return is_priv;
- case 3:
- return true;
- default:
- g_assert_not_reached();
- }
-}
-
/*
* What kind of stack write are we doing? This affects how exceptions
* generated during the stacking are treated.
@@ -12119,7 +12085,7 @@ static bool v8m_is_sau_exempt(CPUARMState *env,
(address >= 0xe00ff000 && address <= 0xe00fffff);
}
-static void v8m_security_lookup(CPUARMState *env, uint32_t address,
+void v8m_security_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
V8M_SAttributes *sattrs)
{
@@ -12226,7 +12192,7 @@ static void v8m_security_lookup(CPUARMState *env,
uint32_t address,
}
}
-static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, MemTxAttrs *txattrs,
int *prot, bool *is_subpage,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 11bfdba512..232d963875 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -892,6 +892,27 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
}
}
+/**
+ * v7m_cpacr_pass:
+ * Return true if the v7M CPACR permits access to the FPU for the specified
+ * security state and privilege level.
+ */
+static inline bool v7m_cpacr_pass(CPUARMState *env,
+ bool is_secure, bool is_priv)
+{
+ switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
+ case 0:
+ case 2: /* UNPREDICTABLE: we treat like 0 */
+ return false;
+ case 1:
+ return is_priv;
+ case 3:
+ return true;
+ default:
+ g_assert_not_reached();
+ }
+}
+
/**
* aarch32_mode_name(): Return name of the AArch32 CPU mode
* @psr: Program Status Register indicating CPU mode
@@ -988,6 +1009,27 @@ static inline int exception_target_el(CPUARMState *env)
#ifndef CONFIG_USER_ONLY
+/* Security attributes for an address, as returned by v8m_security_lookup. */
+typedef struct V8M_SAttributes {
+ bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
+ bool ns;
+ bool nsc;
+ uint8_t sregion;
+ bool srvalid;
+ uint8_t iregion;
+ bool irvalid;
+} V8M_SAttributes;
+
+void v8m_security_lookup(CPUARMState *env, uint32_t address,
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
+ V8M_SAttributes *sattrs);
+
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
+ hwaddr *phys_ptr, MemTxAttrs *txattrs,
+ int *prot, bool *is_subpage,
+ ARMMMUFaultInfo *fi, uint32_t *mregion);
+
/* Cacheability and shareability attributes for a memory access */
typedef struct ARMCacheAttrs {
unsigned int attrs:8; /* as in the MAIR register encoding */
--
2.20.1
- [Qemu-devel] [PATCH v3 10/27] target/arm: Move CPU state dumping routines to cpu.c, (continued)
- [Qemu-devel] [PATCH v3 10/27] target/arm: Move CPU state dumping routines to cpu.c, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 09/27] target/arm: Move the DC ZVA helper into op_helper, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 14/27] target/arm/vfp_helper: Move code around, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 13/27] target/arm: Move debug routines to debug_helper.c, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 12/27] target/arm: Move TLB related routines to tlb_helper.c, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 15/27] target/arm/vfp_helper: Extract vfp_set_fpscr_to_host(), Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 16/27] target/arm/vfp_helper: Extract vfp_set_fpscr_from_host(), Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 20/27] target/arm: Declare arm_log_exception() function publicly, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 17/27] target/arm/vfp_helper: Restrict the SoftFloat use to TCG, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 21/27] target/arm: Declare some M-profile functions publicly,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v3 19/27] target/arm: Restrict PSCI to TCG, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [RFC PATCH v3 23/27] target/arm: Restrict pre-ARMv7 cpus to TCG, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 18/27] target/arm: Restrict semi-hosting to TCG, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [RFC PATCH v3 24/27] target/arm: Do not build pre-ARMv7 cpus when using KVM, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [RFC PATCH v3 25/27] target/arm: Restrict R and M profiles to TCG, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [RFC PATCH v3 26/27] target/arm: Do not build A/M-profile cpus when using KVM, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v3 27/27] target/arm: Do not build TCG objects when TCG is off, Philippe Mathieu-Daudé, 2019/07/01