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[Qemu-devel] [PATCH v4 6/8] RFC target/arm: Restrict R and M profiles to
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v4 6/8] RFC target/arm: Restrict R and M profiles to TCG |
Date: |
Mon, 1 Jul 2019 21:49:40 +0200 |
KVM is only able to run A profile cpus.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
target/arm/cpu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 290ef16e52..a0934a47ee 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -453,7 +453,9 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
return ret;
}
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if (!defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)) \
+ && defined(CONFIG_TCG)
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -1855,8 +1857,6 @@ static void cortex_m0_initfn(Object *obj)
cpu->midr = 0x410cc200;
}
-#endif
-
static void cortex_m3_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -2010,6 +2010,8 @@ static void cortex_r5f_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000011;
}
+#endif
+
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2491,7 +2493,6 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "arm1176", .initfn = arm1176_initfn },
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
{ .name = "cortex-m0", .initfn = cortex_m0_initfn,
-#endif
.class_init = arm_v7m_class_init },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
.class_init = arm_v7m_class_init },
@@ -2501,6 +2502,7 @@ static const ARMCPUInfo arm_cpus[] = {
.class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
+#endif
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
--
2.20.1
- [Qemu-devel] [PATCH v4 0/8] Support disabling TCG on ARM, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v4 1/8] target/arm: Move debug routines to debug_helper.c, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v4 8/8] target/arm: Do not build TCG objects when TCG is off, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v4 4/8] RFC target/arm: Restrict pre-ARMv7 cpus to TCG, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v4 7/8] RFC target/arm: Do not build A/M-profile cpus when using KVM, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v4 3/8] target/arm/helper: Move M profile routines to m_helper.c, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v4 6/8] RFC target/arm: Restrict R and M profiles to TCG,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v4 2/8] target/arm: Restrict semi-hosting to TCG, Philippe Mathieu-Daudé, 2019/07/01
- [Qemu-devel] [PATCH v4 5/8] RFC target/arm: Do not build pre-ARMv7 cpus when using KVM, Philippe Mathieu-Daudé, 2019/07/01
- Re: [Qemu-devel] [PATCH v4 0/8] Support disabling TCG on ARM, Peter Maydell, 2019/07/02
- Re: [Qemu-devel] [PATCH v4 0/8] Support disabling TCG on ARM, no-reply, 2019/07/02
- Re: [Qemu-devel] [PATCH v4 0/8] Support disabling TCG on ARM, no-reply, 2019/07/03