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[Qemu-devel] [PULL 14/32] target/riscv: Add the privledge spec version 1
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0 |
Date: |
Wed, 3 Jul 2019 01:40:30 -0700 |
From: Alistair Francis <address@hidden>
Add support for the ratified RISC-V privledge spec.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_privileged.inc.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5eb9cab2ad62..d559d28bcda8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,6 +81,7 @@ enum {
#define USER_VERSION_2_02_0 0x00020200
#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
+#define PRIV_VERSION_1_11_0 0x00011100
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c
b/target/riscv/insn_trans/trans_privileged.inc.c
index 664d6ba3f2cc..c5e4b3e49a3e 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -90,7 +90,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
+ if (ctx->priv_ver >= PRIV_VERSION_1_10_0) {
gen_helper_tlb_flush(cpu_env);
return true;
}
--
2.21.0
- [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access, (continued)
- [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 08/32] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 13/32] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 15/32] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 18/32] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 19/32] target/riscv: Remove user version information, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 27/32] disas/riscv: Fix `rdinstreth` constraint, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 29/32] riscv: sifive_u: Update the plic hart config to support multicore, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 21/32] RISC-V: Add support for the Zifencei extension, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 25/32] riscv: virt: Add cpu-topology DT node., Palmer Dabbelt, 2019/07/03