Re: [Qemu-devel] [RISU RFC PATCH v2 06/14] x86.risu: add MMX instructions

[Jan Bobek]

On 7/3/19 5:35 PM, Richard Henderson wrote:
> On 7/1/19 6:35 AM, Jan Bobek wrote:
>> Add an x86 configuration file with all MMX instructions.
>>
>> Signed-off-by: Jan Bobek <address@hidden>
>> ---
>>  x86.risu | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 96 insertions(+)
>>  create mode 100644 x86.risu
> 
> Note that most of these MMX instructions affect the FPU, not the vector unit.
> We would want to extend risu again to handle this.  You'd also need to seed 
> the
> FPU with random data.
> 
> I was thinking for a moment that this is really beyond what you've signed up
> for, but on second thoughts it's not.  Decoding SSE is really tangled with
> decoding MMX, via the 0x66 prefix, and you'll want to be able to verify that
> you don't regress.

Honestly, I added MMX instructions just for completeness; I figured it can't
hurt, and you can always filter them out via command-line switches. You have
a point with the regression testing, though...

>> +# State Management Instructions
>> +EMMS            MMX     00001111 01110111 !emit { }
> 
> I'm not sure this is really testable, because of the state change.  But we'll
> see what happens with the aforementioned dumping.
> 
>> +# Arithmetic Instructions
>> +PADDB           MMX     00001111 11111100 !emit { modrm(); mem(size => 8); }
>> +PADDW           MMX     00001111 11111101 !emit { modrm(); mem(size => 8); }
>> +PADDD           MMX     00001111 11111110 !emit { modrm(); mem(size => 8); }
>> +PADDQ           MMX     00001111 11010100 !emit { modrm(); mem(size => 8); }

Not this one, at least according to the Intel docs:

NP 0F D4 /r: PADDQ mm, mm/m64          (MMX)
66 0F D4 /r: PADDQ xmm1, xmm2/m128     (SSE2)

The SSE2 version is added in a later patch.

-Jan

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