[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 09/10] target/arm: Set VFP-related MVFR0 fields for a
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/10] target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026 |
Date: |
Mon, 15 Jul 2019 14:42:10 +0100 |
The ARMv5 architecture didn't specify detailed per-feature ID
registers. Now that we're using the MVFR0 register fields to
gate the existence of VFP instructions, we need to set up
the correct values in the cpu->isar structure so that we still
provide an FPU to the guest.
This fixes a regression in the arm926 and arm1026 CPUs, which
are the only ones that both have VFP and are ARMv5 or earlier.
This regression was introduced by the VFP refactoring, and more
specifically by commits 1120827fa182f0e76 and 266bd25c485597c,
which accidentally disabled VFP short-vector support and
double-precision support on these CPUs.
Fixes: 1120827fa182f0e
Fixes: 266bd25c485597c
Fixes: https://bugs.launchpad.net/qemu/+bug/1836192
Reported-by: Christophe Lyon <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Christophe Lyon <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ad164a773b2..1959467fdc8 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1666,6 +1666,12 @@ static void arm926_initfn(Object *obj)
* set the field to indicate Jazelle support within QEMU.
*/
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ /*
+ * Similarly, we need to set MVFR0 fields to enable double precision
+ * and short vector support even though ARMv5 doesn't have this register.
+ */
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
}
static void arm946_initfn(Object *obj)
@@ -1702,6 +1708,12 @@ static void arm1026_initfn(Object *obj)
* set the field to indicate Jazelle support within QEMU.
*/
cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ /*
+ * Similarly, we need to set MVFR0 fields to enable double precision
+ * and short vector support even though ARMv5 doesn't have this register.
+ */
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
{
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
--
2.20.1
- [Qemu-devel] [PULL 00/10] target-arm queue, Peter Maydell, 2019/07/15
- [Qemu-devel] [PULL 02/10] hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs, Peter Maydell, 2019/07/15
- [Qemu-devel] [PULL 01/10] target/arm: report ARMv8-A FP support for AArch32 -cpu max, Peter Maydell, 2019/07/15
- [Qemu-devel] [PULL 03/10] hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory, Peter Maydell, 2019/07/15
- [Qemu-devel] [PULL 07/10] hw/arm/virt: Fix non-secure flash mode, Peter Maydell, 2019/07/15
- [Qemu-devel] [PULL 05/10] hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO, Peter Maydell, 2019/07/15
- [Qemu-devel] [PULL 04/10] hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[], Peter Maydell, 2019/07/15
- [Qemu-devel] [PULL 06/10] hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO, Peter Maydell, 2019/07/15
- [Qemu-devel] [PULL 09/10] target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026,
Peter Maydell <=
- [Qemu-devel] [PULL 08/10] pl031: Correctly migrate state when using -rtc clock=host, Peter Maydell, 2019/07/15
- [Qemu-devel] [PULL 10/10] target/arm: NS BusFault on vector table fetch escalates to NS HardFault, Peter Maydell, 2019/07/15
- Re: [Qemu-devel] [PULL 00/10] target-arm queue, Peter Maydell, 2019/07/15
- Re: [Qemu-devel] [PULL 00/10] target-arm queue, no-reply, 2019/07/15
- Re: [Qemu-devel] [PULL 00/10] target-arm queue, no-reply, 2019/07/16