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Re: [Qemu-devel] [PATCH for-4.2 03/24] target/arm: Install ASIDs for lon
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [PATCH for-4.2 03/24] target/arm: Install ASIDs for long-form from EL1 |
Date: |
Mon, 22 Jul 2019 16:28:22 +0100 |
User-agent: |
mu4e 1.3.3; emacs 27.0.50 |
Richard Henderson <address@hidden> writes:
> In addition to providing the core with the current ASID, this minimizes
> both the number of flushes due to non-changing ASID as well as the set
> of mmu_idx that are affected by each flush.
>
> In particular, updates to the secure mode registers flushes only the
> relevant secure mode mmu_idx's, and similarly non-secure updates only
> affect non-secure mmu_idx's.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/helper.c | 73 +++++++++++++++++++++++++++++----------------
> 1 file changed, 48 insertions(+), 25 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 20f8728be1..0f21a077de 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3327,6 +3327,36 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
> REGINFO_SENTINEL
> };
>
> +/* Called after a change to any of TTBR*_EL1 or TTBCR_EL1. */
> +static void update_lpae_el1_asid(CPUARMState *env, int secure)
> +{
> + CPUState *cs = env_cpu(env);
> + uint64_t ttbr0, ttbr1, ttcr;
> + int asid, idxmask;
> +
> + switch (secure) {
> + case ARM_CP_SECSTATE_S:
> + ttbr0 = env->cp15.ttbr0_s;
> + ttbr1 = env->cp15.ttbr1_s;
> + ttcr = env->cp15.tcr_el[3].raw_tcr;
> + /* Note that cp15.ttbr0_s == cp15.ttbr0_el[3], so S1E3 is affected.
> */
> + /* ??? Secure EL3 really using the ASID field? Doesn't make sense.
> */
> + idxmask = ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0 |
> ARMMMUIdxBit_S1E3;
> + break;
> + case ARM_CP_SECSTATE_NS:
> + ttbr0 = env->cp15.ttbr0_ns;
> + ttbr1 = env->cp15.ttbr1_ns;
> + ttcr = env->cp15.tcr_el[1].raw_tcr;
> + idxmask = ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + asid = extract64(ttcr & TTBCR_A1 ? ttbr1 : ttbr0, 48, 16);
> +
> + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0);
> +}
> +
> static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> @@ -3363,18 +3393,16 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env,
> const ARMCPRegInfo *ri,
> static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = env_archcpu(env);
> TCR *tcr = raw_ptr(env, ri);
>
> - if (arm_feature(env, ARM_FEATURE_LPAE)) {
> - /* With LPAE the TTBCR could result in a change of ASID
> - * via the TTBCR.A1 bit, so do a TLB flush.
> - */
> - tlb_flush(CPU(cpu));
> - }
> /* Preserve the high half of TCR_EL1, set via TTBCR2. */
> value = deposit64(tcr->raw_tcr, 0, 32, value);
> vmsa_ttbcr_raw_write(env, ri, value);
> +
> + if (arm_feature(env, ARM_FEATURE_LPAE)) {
> + /* The A1 bit controls which ASID is active. */
> + update_lpae_el1_asid(env, ri->secure);
> + }
> }
>
> static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
> @@ -3392,24 +3420,19 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const
> ARMCPRegInfo *ri)
> static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = env_archcpu(env);
> - TCR *tcr = raw_ptr(env, ri);
> -
> - /* For AArch64 the A1 bit could result in a change of ASID, so TLB
> flush. */
> - tlb_flush(CPU(cpu));
> - tcr->raw_tcr = value;
> + raw_write(env, ri, value);
> + /* The A1 bit controls which ASID is active. */
> + update_lpae_el1_asid(env, ri->secure);
> }
>
> -static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> - uint64_t value)
> +static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
Why the rename here? It would make sense if it was only EL1 writes but
the lpae_cp_reginfo doesn't seem to use that nomclature (unless we
should fix .name for those as well?).
> {
> - /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
> - if (cpreg_field_is_64bit(ri) &&
> - extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
> - ARMCPU *cpu = env_archcpu(env);
> - tlb_flush(CPU(cpu));
> - }
> raw_write(env, ri, value);
> + if (cpreg_field_is_64bit(ri)) {
> + /* The LPAE format (64-bit write) contains an ASID field. */
> + update_lpae_el1_asid(env, ri->secure);
> + }
> }
>
> static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -3455,12 +3478,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
> .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0,
> },
> { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
> - .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
> + .access = PL1_RW, .writefn = vmsa_ttbr_el1_write, .resetvalue = 0,
> .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
> offsetof(CPUARMState, cp15.ttbr0_ns) } },
> { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
> - .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
> + .access = PL1_RW, .writefn = vmsa_ttbr_el1_write, .resetvalue = 0,
> .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
> offsetof(CPUARMState, cp15.ttbr1_ns) } },
> { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
> @@ -3715,12 +3738,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
> .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
> .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
> offsetof(CPUARMState, cp15.ttbr0_ns) },
> - .writefn = vmsa_ttbr_write, },
> + .writefn = vmsa_ttbr_el1_write, },
> { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
> .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
> .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
> offsetof(CPUARMState, cp15.ttbr1_ns) },
> - .writefn = vmsa_ttbr_write, },
> + .writefn = vmsa_ttbr_el1_write, },
> REGINFO_SENTINEL
> };
Otherwise:
Reviewed-by: Alex Bennée <address@hidden>
--
Alex Bennée
- [Qemu-devel] [PATCH for-4.2 00/24] target/arm: Implement ARMv8.1-VHE, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 01/24] cputlb: Add tlb_set_asid_for_mmuidx, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 02/24] cputlb: Add tlb_flush_asid_by_mmuidx and friends, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 03/24] target/arm: Install ASIDs for long-form from EL1, Richard Henderson, 2019/07/19
- Re: [Qemu-devel] [PATCH for-4.2 03/24] target/arm: Install ASIDs for long-form from EL1,
Alex Bennée <=
- [Qemu-devel] [PATCH for-4.2 04/24] target/arm: Install ASIDs for short-form from EL1, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 05/24] target/arm: Install ASIDs for EL2, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 11/24] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 14/24] target/arm: Simplify tlb_force_broadcast alternatives, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 18/24] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2019/07/19