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Re: [Qemu-devel] [PATCH for-4.2 10/24] target/arm: Update CNTVCT_EL0 for
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [PATCH for-4.2 10/24] target/arm: Update CNTVCT_EL0 for VHE |
Date: |
Wed, 24 Jul 2019 15:47:48 +0100 |
User-agent: |
mu4e 1.3.3; emacs 27.0.50 |
Richard Henderson <address@hidden> writes:
> The virtual offset may be 0 depending on EL, E2H and TGE.
>
> Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
> ---
> target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++---
> 1 file changed, 37 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index da2e0627b2..3124d682a2 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -2484,9 +2484,31 @@ static uint64_t gt_cnt_read(CPUARMState *env, const
> ARMCPRegInfo *ri)
> return gt_get_countervalue(env);
> }
>
> +static uint64_t gt_virt_cnt_offset(CPUARMState *env)
> +{
> + uint64_t hcr;
> +
> + switch (arm_current_el(env)) {
> + case 2:
> + hcr = arm_hcr_el2_eff(env);
> + if (hcr & HCR_E2H) {
> + return 0;
> + }
> + break;
> + case 0:
> + hcr = arm_hcr_el2_eff(env);
> + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
> + return 0;
> + }
> + break;
> + }
> +
> + return env->cp15.cntvoff_el2;
> +}
> +
> static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> - return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
> + return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
> }
>
> static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -2501,7 +2523,13 @@ static void gt_cval_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
> int timeridx)
> {
> - uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
> + uint64_t offset = 0;
> +
> + switch (timeridx) {
> + case GTIMER_VIRT:
> + offset = gt_virt_cnt_offset(env);
> + break;
> + }
>
> return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
> (gt_get_countervalue(env) - offset));
> @@ -2511,7 +2539,13 @@ static void gt_tval_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> int timeridx,
> uint64_t value)
> {
> - uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
> + uint64_t offset = 0;
> +
> + switch (timeridx) {
> + case GTIMER_VIRT:
> + offset = gt_virt_cnt_offset(env);
> + break;
> + }
>
> trace_arm_gt_tval_write(timeridx, value);
> env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
--
Alex Bennée
- Re: [Qemu-devel] [PATCH for-4.2 05/24] target/arm: Install ASIDs for EL2, (continued)
- [Qemu-devel] [PATCH for-4.2 11/24] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 14/24] target/arm: Simplify tlb_force_broadcast alternatives, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 18/24] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 17/24] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 13/24] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 10/24] target/arm: Update CNTVCT_EL0 for VHE, Richard Henderson, 2019/07/19
- Re: [Qemu-devel] [PATCH for-4.2 10/24] target/arm: Update CNTVCT_EL0 for VHE,
Alex Bennée <=
- [Qemu-devel] [PATCH for-4.2 21/24] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 09/24] target/arm: Add TTBR1_EL2, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 12/24] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 22/24] target/arm: Update regime_is_user for EL2&0, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 06/24] target/arm: Define isar_feature_aa64_vh, Richard Henderson, 2019/07/19
- [Qemu-devel] [PATCH for-4.2 19/24] target/arm: Install asids for E2&0 translation regime, Richard Henderson, 2019/07/19