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Re: [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg,
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm) |
Date: |
Mon, 29 Jul 2019 16:25:02 +0100 |
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<address@hidden> wrote:
>
> Do these all in one lump because these are all logically intertwined.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/translate.c | 747 ++++++++++++++++++++---------------------
> target/arm/a32.decode | 84 +++++
> target/arm/t32.decode | 91 +++++
> 3 files changed, 536 insertions(+), 386 deletions(-
I'm afraid this patch is too big for me to digest :-(
I just spent about half an hour trying to figure out whether
the changes just to the thumb dp-immediate insns were right
and didn't manage to work through it all.
> +
> +# Data-processing (immediate)
> +
> +%t32extrot 26:1 12:3 0:8 !function=t32_expandimm_rot
> +%t32extimm 26:1 12:3 0:8 !function=t32_expandimm_imm
> +
> +@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \
> + &s_rri_rot imm=%t32extimm rot=%t32extrot
> +@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \
> + &s_rri_rot imm=%t32extimm rot=%t32extrot rn=0
> +@S_xri_rot ....... .... . rn:4 . ... .... ........ \
> + &s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0
> +
> +{
> + TST_rri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot
> + AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot
> +}
> +BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot
> +{
> + MOV_rri 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot
> + ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot
> +}
> +{
> + MVN_rri 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot
> + ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot
> +}
> +{
> + TEQ_rri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot
> + EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot
> +}
> +{
> + CMN_rri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot
> + ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot
> +}
> +ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot
> +SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot
> +{
> + CMP_rri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot
> + SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot
> +}
> +RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
> --
Why do we split it up into all these different kinds of patterns
where some insns have special cases for rn==15 and some have
special cases for rd==15 ?
The legacy decoder doesn't seem to do that -- it treats everything
the same.
thanks
-- PMM
- [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg, (continued)
- [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm), Richard Henderson, 2019/07/26
- Re: [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm),
Peter Maydell <=
- [Qemu-devel] [PATCH 23/67] target/arm: Convert Synchronization primitives, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 28/67] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/07/26