[Qemu-devel] [RFC PATCH v1 00/22] reimplement (some) x86 vector instructions using tcg-gvec

[Jan Bobek]

This patch series is an early work-in-progress snapshot of my efforts
to utilize the TCG gvec infrastracture in x86 frontend. Only a handful
of instructions have been converted (those which have a direct gvec
equivalent).

The dispatch switch for the converted instructions is sort of hacked
into gen_sse; this is obviously intended for development only.
Eventually, everything that follows this switch will be removed,
along with the SSE tables and all that goes along with it.

Cheers,
  -Jan

Jan Bobek (18):
  target/i386: introduce gen_ld_modrm_* helpers
  target/i386: introduce gen_gvec_ld_modrm_* helpers
  target/i386: add vector register file alignment constraints
  target/i386: reimplement (V)PAND, (V)ANDPS, (V)ANDPD
  target/i386: reimplement (V)POR, (V)ORPS, (V)ORPD
  target/i386: reimplement (V)PXOR, (V)XORPS, (V)XORPD
  target/i386: reimplement (V)PANDN, (V)ANDNPS, (V)ANDNPD
  target/i386: reimplement (V)PADD(B,W,D,Q)
  target/i386: reimplement (V)PSUB(B,W,D,Q)
  target/i386: reimplement (V)PADDS(B,W)
  target/i386: reimplement (V)PADDUS(B,W)
  target/i386: reimplement (V)PSUBS(B,W)
  target/i386: reimplement (V)PSUBUS(B,W)
  target/i386: reimplement (V)PMINSW
  target/i386: reimplement (V)PMINUB
  target/i386: reimplement (V)PMAXSW
  target/i386: reimplement (V)PMAXUB
  target/i386: reimplement (V)P(EQ,CMP)(B,W,D)

Richard Henderson (4):
  target/i386: Push rex_r into DisasContext
  target/i386: Push rex_w into DisasContext
  target/i386: Use prefix, aflag and dflag from DisasContext
  target/i386: Simplify gen_exception arguments

 target/i386/cpu.h            |   6 +-
 target/i386/ops_sse.h        |  65 ---
 target/i386/ops_sse_header.h |  39 --
 target/i386/translate.c      | 990 +++++++++++++++++++++++++----------
 4 files changed, 723 insertions(+), 377 deletions(-)

-- 
2.20.1