Re: [Qemu-devel] [RFC PATCH v2 23/39] target/i386: introduce instruction translator macros

[Jan Bobek]

On 8/13/19 2:30 AM, Richard Henderson wrote:
> On 8/10/19 5:12 AM, Jan Bobek wrote:
>> +#define CASES_LEG_NP_0F_W0(opcode)              \
>> +    case opcode | M_0F | W_0:
>> +#define CASES_LEG_NP_0F_W1(opcode)              \
>> +    case opcode | M_0F | W_1:
>> +#define CASES_LEG_F3_0F_W0(opcode)              \
>> +    case opcode | M_0F | P_F3 | W_0:
>> +#define CASES_LEG_F3_0F_W1(opcode)              \
>> +    case opcode | M_0F | P_F3 | W_1:
>> +
>> +#define LEG(p, m, w)                            \
>> +    CASES_LEG_ ## p ## _ ## m ## _W ## w
>> +#define INSN(mnem, cases, opcode, feat)         \
>> +    cases(opcode)                               \
> 
> It appears as if you don't need the CASES_* macros here.
> 
> #define LEG(p, m, w, op) \
>    case P_##p | M_##m | W_##2 | op
> 
> #define INSN(mnem, leg, feat) \
>    leg: translate_insn(env, s, CK_CPUID_##feat, gen_insn(mnem));
> 
> so long as P_NP is in the enumeration above with value 0.
> 
> Unless there's some other reason that opcode needs to stay separate?

I was thinking ahead with the CASES_* macros here: if I have LIG
and/or WIG in the VEX prefix, I'll need more than one case label,
but only one label in other cases. However, that's not a reason
for the opcode to be separate, and I think I like it stashed with
the rest of the prefix fields better.

-Jan

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