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[Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branc
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branches, Supervisor call |
Date: |
Mon, 19 Aug 2019 14:37:48 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 26 +++-----------------------
target/arm/t16.decode | 12 ++++++++++++
2 files changed, 15 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5f876290ba..941266df14 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10599,7 +10599,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- uint32_t val, op, rm, rd, shift, cond;
+ uint32_t val, op, rm, rd, shift;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -10738,28 +10738,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
}
break;
- case 13:
- /* conditional branch or swi */
- cond = (insn >> 8) & 0xf;
- if (cond == 0xe)
- goto undef;
-
- if (cond == 0xf) {
- /* swi */
- gen_set_pc_im(s, s->base.pc_next);
- s->svc_imm = extract32(insn, 0, 8);
- s->base.is_jmp = DISAS_SWI;
- break;
- }
- /* generate a conditional jump to next instruction */
- arm_skip_unless(s, cond);
-
- /* jump to the offset */
- val = read_pc(s);
- offset = ((int32_t)insn << 24) >> 24;
- val += offset << 1;
- gen_jmp(s, val);
- break;
+ case 13: /* conditional branch or swi, in decodetree */
+ goto illegal_op;
case 14:
if (insn & (1 << 11)) {
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index d731402036..98d60952a1 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -28,11 +28,13 @@
&rr !extern rd rm
&ri !extern rd imm
&r !extern rm
+&i !extern imm
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
&ldst_block !extern rn i b u w list
&setend !extern E
&cps !extern mode imod M A I F
+&ci !extern cond imm
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@@ -231,3 +233,13 @@ STM 1011 010 ......... \
&ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
LDM_t16 1011 110 ......... \
&ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
+
+# Conditional branches, Supervisor call
+
+%imm8_0x2 0:s8 !function=times_2
+
+{
+ UDF 1101 1110 ---- ----
+ SVC 1101 1111 imm:8 &i
+ B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2
+}
--
2.17.1
- [Qemu-devel] [PATCH v2 55/68] target/arm: Convert T16, extract, (continued)
- [Qemu-devel] [PATCH v2 55/68] target/arm: Convert T16, extract, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 58/68] target/arm: Convert T16, nop hints, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 50/68] target/arm: Convert T16 add/sub (3 low, 2 low and imm), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 56/68] target/arm: Convert T16, Change processor state, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 57/68] target/arm: Convert T16, Reverse bytes, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branches, Supervisor call,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 59/68] target/arm: Split gen_nop_hint, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 60/68] target/arm: Convert T16, push and pop, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 62/68] target/arm: Convert T16, Miscellaneous 16-bit instructions, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 64/68] target/arm: Convert T16, load (literal), Richard Henderson, 2019/08/19