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Re: [Qemu-devel] [PATCH v5 12/30] riscv: sifive_e: Drop sifive_mmio_emul
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v5 12/30] riscv: sifive_e: Drop sifive_mmio_emulate() |
Date: |
Mon, 26 Aug 2019 21:36:41 +0000 |
On Thu, 2019-08-22 at 22:10 -0700, Bin Meng wrote:
> Use create_unimplemented_device() instead.
>
> Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
>
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common
> place"
> - new patch "riscv: sifive_e: Drop sifive_mmio_emulate()"
>
> hw/riscv/sifive_e.c | 23 ++++++++---------------
> 1 file changed, 8 insertions(+), 15 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 2d67670..040d59f 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -37,6 +37,7 @@
> #include "hw/loader.h"
> #include "hw/sysbus.h"
> #include "hw/char/serial.h"
> +#include "hw/misc/unimp.h"
> #include "target/riscv/cpu.h"
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/sifive_plic.h"
> @@ -74,14 +75,6 @@ static const struct MemmapEntry {
> [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
> };
>
> -static void sifive_mmio_emulate(MemoryRegion *parent, const char
> *name,
> - uintptr_t offset, uintptr_t length)
> -{
> - MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
> - memory_region_init_ram(mock_mmio, NULL, name, length,
> &error_fatal);
> - memory_region_add_subregion(parent, offset, mock_mmio);
> -}
> -
> static void riscv_sifive_e_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
> @@ -172,7 +165,7 @@ static void
> riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
> memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
> SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
> + create_unimplemented_device("riscv.sifive.e.aon",
> memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
>
> @@ -199,19 +192,19 @@ static void
> riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
>
> sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
> serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic),
> SIFIVE_E_UART0_IRQ));
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
> + create_unimplemented_device("riscv.sifive.e.qspi0",
> memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
> + create_unimplemented_device("riscv.sifive.e.pwm0",
> memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
> sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
> serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic),
> SIFIVE_E_UART1_IRQ));
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
> + create_unimplemented_device("riscv.sifive.e.qspi1",
> memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
> + create_unimplemented_device("riscv.sifive.e.pwm1",
> memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
> + create_unimplemented_device("riscv.sifive.e.qspi2",
> memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
> + create_unimplemented_device("riscv.sifive.e.pwm2",
> memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
>
> /* Flash memory */
- [Qemu-devel] [PATCH v5 24/30] riscv: sifive_u: Change UART node name in device tree, (continued)
- [Qemu-devel] [PATCH v5 24/30] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 25/30] riscv: roms: Update default bios for sifive_u machine, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 30/30] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 28/30] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/23
- Re: [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Alistair Francis, 2019/08/23
- Re: [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Alistair Francis, 2019/08/23
- Message not available
- Re: [Qemu-devel] [PATCH v5 12/30] riscv: sifive_e: Drop sifive_mmio_emulate(),
Alistair Francis <=