[Qemu-devel] [PATCH 1/2] target/i386: Add support for save PEBS registers

[Luwei Kang]

Intel processor introduce some hardware extensions that output PEBS record
to Intel PT buffer instead of DS area, so PEBS can be enabled in KVM guest
by PEBS output Intel PT. This patch adds a section for PEBS which use for
saves PEBS registers when the value is no-zero.

Signed-off-by: Luwei Kang <address@hidden>
---
 target/i386/cpu.h     |  8 ++++++++
 target/i386/machine.c | 41 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5f6e3a0..d7cec36 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -409,6 +409,10 @@ typedef enum X86Seg {
 #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
 
+#define MSR_IA32_PEBS_ENABLE            0x3f1
+#define MSR_RELOAD_FIXED_CTR0           0x1309
+#define MSR_RELOAD_PMC0                 0x14c1
+
 #define MSR_MC0_CTL                     0x400
 #define MSR_MC0_STATUS                  0x401
 #define MSR_MC0_ADDR                    0x402
@@ -1291,6 +1295,10 @@ typedef struct CPUX86State {
     uint64_t msr_rtit_cr3_match;
     uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
 
+    uint64_t msr_pebs_enable;
+    uint64_t msr_reload_fixed_ctr[MAX_FIXED_COUNTERS];
+    uint64_t msr_reload_pmc[MAX_GP_COUNTERS];
+
     /* exception/interrupt handling */
     int error_code;
     int exception_is_int;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 2767b30..334d703 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -1274,6 +1274,46 @@ static const VMStateDescription vmstate_efer32 = {
 };
 #endif
 
+static bool pebs_enable_needed(void *opaque)
+{
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
+    int i;
+
+    if (env->msr_pebs_enable) {
+        return true;
+    }
+
+    for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
+        if (env->msr_reload_fixed_ctr[i]) {
+            return true;
+        }
+    }
+
+    for (i = 0; i < MAX_GP_COUNTERS; i++) {
+        if (env->msr_reload_pmc[i]) {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static const VMStateDescription vmstate_msr_pebs = {
+    .name = "cpu/pebs",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = pebs_enable_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(env.msr_pebs_enable, X86CPU),
+        VMSTATE_UINT64_ARRAY(env.msr_reload_fixed_ctr, X86CPU,
+                                MAX_FIXED_COUNTERS),
+        VMSTATE_UINT64_ARRAY(env.msr_reload_pmc, X86CPU,
+                                MAX_GP_COUNTERS),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 VMStateDescription vmstate_x86_cpu = {
     .name = "cpu",
     .version_id = 12,
@@ -1407,6 +1447,7 @@ VMStateDescription vmstate_x86_cpu = {
 #ifdef CONFIG_KVM
         &vmstate_nested_state,
 #endif
+        &vmstate_msr_pebs,
         NULL
     }
 };
-- 
1.8.3.1