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[PATCH v3 0/3] target/riscv: Expose "priv" register for GDB
From: |
Jonathan Behrens |
Subject: |
[PATCH v3 0/3] target/riscv: Expose "priv" register for GDB |
Date: |
Mon, 7 Oct 2019 20:13:15 -0400 |
The third patch in this series makes the priv virtual register writitable. I'm
not entirely sure this is a good idea, so I split it out into its own patch. In
particular, this change will conflict with the hypervisor extension work which
assumes that the privilege mode does not change in unexpected cases.
As pointed out in a previous version of this series, GDB actually contains some
support already for the accessing the privilege mode via a virtual "priv"
register, including to convert the values into human readable forms:
(gdb) info reg priv
priv 0x3 prv:3 [Machine]
Changlog V3:
- Break patch into series
- Make priv a virtual register
Changelog V2:
- Use PRV_H and PRV_S instead of integer literals
Jonathan Behrens (3)
target/riscv: Tell gdbstub the correct number of CSRs
target/riscv: Expose priv register for GDB for reads
target/riscv: Make the priv register writable by GDB
configure | 4 ++--
gdb-xml/riscv-32bit-virtual.xml | 11 +++++++++++
gdb-xml/riscv-64bit-virtual.xml | 11 +++++++++++
target/riscv/gdbstub.c | 36 ++++++++++++++++++++++++++++++++++--
4 files changed, 58 insertions(+), 4 deletions(-)
- [PATCH v3 0/3] target/riscv: Expose "priv" register for GDB,
Jonathan Behrens <=