This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support yet. PC is set to 0 at reset.
the patches include the following
1. just a basic 8bit AVR CPU, without instruction decoding or translation
2. CPU features which allow define the following 8bit AVR cores
avr1
avr2 avr25
avr3 avr31 avr35
avr4
avr5 avr51
avr6
xmega2 xmega4 xmega5 xmega6 xmega7
3. a definition of sample machine with SRAM, FLASH and CPU which allows to
execute simple code
4. encoding for all AVR instructions
5. interrupt handling
6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
7. a decoder which given an opcode decides what istruction it is
8. translation of AVR instruction into TCG
9. all features together
Michael Rolnik (7):
target/avr: Add outward facing interfaces and core CPU logic
target/avr: Add instruction helpers
target/avr: Add instruction decoding
target/avr: Add instruction translation
target/avr: Add example board configuration
target/avr: Register AVR support with the rest of QEMU, the build
system, and the MAINTAINERS file
target/avr: Add tests
Sarah Harris (1):
target/avr: Add limited support for USART and 16 bit timer peripherals