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[PULL 06/23] tcg/ppc: Replace HAVE_ISEL macro with a variable
From: |
Richard Henderson |
Subject: |
[PULL 06/23] tcg/ppc: Replace HAVE_ISEL macro with a variable |
Date: |
Sun, 13 Oct 2019 15:25:27 -0700 |
Previously we've been hard-coding knowledge that Power7 has ISEL, but
it was an optional instruction before that. Use the AT_HWCAP2 bit,
when present, to properly determine support.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc/tcg-target.inc.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 7cb0002c14..db28ae7eb1 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -65,8 +65,7 @@
static tcg_insn_unit *tb_ret_addr;
TCGPowerISA have_isa;
-
-#define HAVE_ISEL have_isa_2_06
+static bool have_isel;
#ifndef CONFIG_SOFTMMU
#define TCG_GUEST_BASE_REG 30
@@ -1100,7 +1099,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType type,
TCGCond cond,
/* If we have ISEL, we can implement everything with 3 or 4 insns.
All other cases below are also at least 3 insns, so speed up the
code generator by not considering them and always using ISEL. */
- if (HAVE_ISEL) {
+ if (have_isel) {
int isel, tab;
tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
@@ -1203,7 +1202,7 @@ static void tcg_out_movcond(TCGContext *s, TCGType type,
TCGCond cond,
tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
- if (HAVE_ISEL) {
+ if (have_isel) {
int isel = tcg_to_isel[cond];
/* Swap the V operands if the operation indicates inversion. */
@@ -1247,7 +1246,7 @@ static void tcg_out_cntxz(TCGContext *s, TCGType type,
uint32_t opc,
} else {
tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
/* Note that the only other valid constant for a2 is 0. */
- if (HAVE_ISEL) {
+ if (have_isel) {
tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
} else if (!const_a2 && a0 == a2) {
@@ -2795,6 +2794,14 @@ static void tcg_target_init(TCGContext *s)
}
#endif
+#ifdef PPC_FEATURE2_HAS_ISEL
+ /* Prefer explicit instruction from the kernel. */
+ have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0;
+#else
+ /* Fall back to knowing Power7 (2.06) has ISEL. */
+ have_isel = have_isa_2_06;
+#endif
+
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
--
2.17.1
- [PULL 00/23] tcg patch queue, Richard Henderson, 2019/10/13
- [PULL 01/23] tcg/ppc: Introduce Altivec registers, Richard Henderson, 2019/10/13
- [PULL 02/23] tcg/ppc: Introduce macro VX4(), Richard Henderson, 2019/10/13
- [PULL 03/23] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC(), Richard Henderson, 2019/10/13
- [PULL 04/23] tcg/ppc: Create TCGPowerISA and have_isa, Richard Henderson, 2019/10/13
- [PULL 05/23] tcg/ppc: Replace HAVE_ISA_2_06, Richard Henderson, 2019/10/13
- [PULL 06/23] tcg/ppc: Replace HAVE_ISEL macro with a variable,
Richard Henderson <=
- [PULL 07/23] tcg/ppc: Enable tcg backend vector compilation, Richard Henderson, 2019/10/13
- [PULL 09/23] tcg/ppc: Add support for vector maximum/minimum, Richard Henderson, 2019/10/13
- [PULL 10/23] tcg/ppc: Add support for vector add/subtract, Richard Henderson, 2019/10/13
- [PULL 08/23] tcg/ppc: Add support for load/store/logic/comparison, Richard Henderson, 2019/10/13
- [PULL 12/23] tcg/ppc: Support vector shift by immediate, Richard Henderson, 2019/10/13
- [PULL 11/23] tcg/ppc: Add support for vector saturated add/subtract, Richard Henderson, 2019/10/13
- [PULL 14/23] tcg/ppc: Support vector dup2, Richard Henderson, 2019/10/13
- [PULL 13/23] tcg/ppc: Support vector multiply, Richard Henderson, 2019/10/13
- [PULL 15/23] tcg/ppc: Enable Altivec detection, Richard Henderson, 2019/10/13
- [PULL 20/23] tcg/ppc: Update vector support for v3.00 Altivec, Richard Henderson, 2019/10/13