[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 45/68] aspeed/timer: Add AST2600 support
From: |
Peter Maydell |
Subject: |
[PULL 45/68] aspeed/timer: Add AST2600 support |
Date: |
Mon, 14 Oct 2019 17:03:41 +0100 |
From: Cédric Le Goater <address@hidden>
The AST2600 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
On the AST2600, it is not configurable via 0x38 (control register 3)
as it is on the AST2500.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/timer/aspeed_timer.h | 1 +
hw/timer/aspeed_timer.c | 51 +++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index 1e0288ebc49..69b1377af01 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -30,6 +30,7 @@
#define TYPE_ASPEED_TIMER "aspeed.timer"
#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
+#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"
#define ASPEED_TIMER_NR_TIMERS 8
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index d70e78a0293..7f73d0c7533 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -538,6 +538,40 @@ static void aspeed_2500_timer_write(AspeedTimerCtrlState
*s, hwaddr offset,
}
}
+static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState *s, hwaddr offset)
+{
+ uint64_t value;
+
+ switch (offset) {
+ case 0x38:
+ case 0x3C:
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ value = 0;
+ break;
+ }
+ return value;
+}
+
+static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
+ uint64_t value)
+{
+ const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF);
+
+ switch (offset) {
+ case 0x3C:
+ aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
+ break;
+
+ case 0x38:
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ break;
+ }
+}
+
static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id)
{
AspeedTimer *t = &s->timers[id];
@@ -674,11 +708,28 @@ static const TypeInfo aspeed_2500_timer_info = {
.class_init = aspeed_2500_timer_class_init,
};
+static void aspeed_2600_timer_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass);
+
+ dc->desc = "ASPEED 2600 Timer";
+ awc->read = aspeed_2600_timer_read;
+ awc->write = aspeed_2600_timer_write;
+}
+
+static const TypeInfo aspeed_2600_timer_info = {
+ .name = TYPE_ASPEED_2600_TIMER,
+ .parent = TYPE_ASPEED_TIMER,
+ .class_init = aspeed_2600_timer_class_init,
+};
+
static void aspeed_timer_register_types(void)
{
type_register_static(&aspeed_timer_info);
type_register_static(&aspeed_2400_timer_info);
type_register_static(&aspeed_2500_timer_info);
+ type_register_static(&aspeed_2600_timer_info);
}
type_init(aspeed_timer_register_types)
--
2.20.1
- [PULL 35/68] target/arm/arm-semi: Factor out implementation of SYS_SEEK, (continued)
- [PULL 35/68] target/arm/arm-semi: Factor out implementation of SYS_SEEK, Peter Maydell, 2019/10/14
- [PULL 36/68] target/arm/arm-semi: Factor out implementation of SYS_FLEN, Peter Maydell, 2019/10/14
- [PULL 37/68] target/arm/arm-semi: Implement support for semihosting feature detection, Peter Maydell, 2019/10/14
- [PULL 38/68] target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension, Peter Maydell, 2019/10/14
- [PULL 39/68] target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension, Peter Maydell, 2019/10/14
- [PULL 40/68] aspeed/wdt: Check correct register for clock source, Peter Maydell, 2019/10/14
- [PULL 41/68] hw/sd/aspeed_sdhci: New device, Peter Maydell, 2019/10/14
- [PULL 44/68] aspeed/timer: Add support for control register 3, Peter Maydell, 2019/10/14
- [PULL 42/68] hw: aspeed_scu: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 43/68] aspeed/timer: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 45/68] aspeed/timer: Add AST2600 support,
Peter Maydell <=
- [PULL 46/68] aspeed/timer: Add support for IRQ status register on the AST2600, Peter Maydell, 2019/10/14
- [PULL 47/68] aspeed/sdmc: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 48/68] aspeed/sdmc: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 50/68] hw: wdt_aspeed: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 49/68] watchdog/aspeed: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 52/68] aspeed/smc: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 51/68] aspeed/smc: Introduce segment operations, Peter Maydell, 2019/10/14
- [PULL 53/68] hw/gpio: Add in AST2600 specific implementation, Peter Maydell, 2019/10/14
- [PULL 55/68] aspeed/i2c: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 54/68] aspeed/i2c: Introduce an object class per SoC, Peter Maydell, 2019/10/14