Re: [PATCH v5 52/55] plugins: make howvec plugin more generic

[Richard Henderson]

On 10/14/19 10:14 AM, Alex Bennée wrote:
>>> -    /* we expect all instructions to by 32 bits for ARM */
>>> -    g_assert(qemu_plugin_insn_size(insn) == 4);
>>> +    /*
>>> +     * We only match the first 32 bits of the instruction which is
>>> +     * fine for most RISCs but a bit limiting for CISC architectures.
>>> +     * They would probably benefit from a more tailored plugin.
>>> +     * However we can fall back to individual instruction counting.
>>> +     */
>>>      opcode = *((uint32_t *)qemu_plugin_insn_data(insn));
>>
>> This totally ignores the endianness of the host.
>> I'm not keen on reading more than the number of
>> bytes in the insn either...
> 
> I guess we can strncpy the data and ensure it is NULL terminated and use
> the "string" hash function instead. It depends if there are many opcode
> strings with NULL's in them.

Um, plenty.  E.g. "adrp x0, ."


r~