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[RFC v2 20/22] intel_iommu: process PASID-based iotlb invalidation
From: |
Liu Yi L |
Subject: |
[RFC v2 20/22] intel_iommu: process PASID-based iotlb invalidation |
Date: |
Thu, 24 Oct 2019 08:34:41 -0400 |
This patch adds the basic PASID-based iotlb (piotlb) invalidation support.
piotlb is used during walking Intel VT-d first-level page table. This patch
only adds the basic processing. Detailed process will be added in next patch.
Cc: Kevin Tian <address@hidden>
Cc: Jacob Pan <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: Yi Sun <address@hidden>
Signed-off-by: Liu Yi L <address@hidden>
---
hw/i386/intel_iommu.c | 57 ++++++++++++++++++++++++++++++++++++++++++
hw/i386/intel_iommu_internal.h | 13 ++++++++++
2 files changed, 70 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index d621455..6cd922f 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3092,6 +3092,59 @@ static bool vtd_process_pasid_desc(IntelIOMMUState *s,
return (ret == 0) ? true : false;
}
+static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
+ uint16_t domain_id,
+ uint32_t pasid)
+{
+}
+
+static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
+ uint32_t pasid, hwaddr addr, uint8_t am, bool ih)
+{
+}
+
+static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
+ VTDInvDesc *inv_desc)
+{
+ uint16_t domain_id;
+ uint32_t pasid;
+ uint8_t am;
+ hwaddr addr;
+
+ if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) ||
+ (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) {
+ error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+
+ domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]);
+ pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]);
+ switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) {
+ case VTD_INV_DESC_PIOTLB_ALL_IN_PASID:
+ vtd_piotlb_pasid_invalidate(s, domain_id, pasid);
+ break;
+
+ case VTD_INV_DESC_PIOTLB_PSI_IN_PASID:
+ am = VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]);
+ addr = (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]);
+ if (am > VTD_MAMV) {
+ error_report_once("Invalid am, > max am value, hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+ vtd_piotlb_page_invalidate(s, domain_id, pasid,
+ addr, am, VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]));
+ break;
+
+ default:
+ error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+ return true;
+}
+
static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
@@ -3206,6 +3259,10 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
break;
case VTD_INV_DESC_PIOTLB:
+ trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]);
+ if (!vtd_process_piotlb_desc(s, &inv_desc)) {
+ return false;
+ }
break;
case VTD_INV_DESC_WAIT:
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 908536c..eddfe54 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -458,6 +458,19 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4)
#define VTD_INV_DESC_PASIDC_GLOBAL (3ULL << 4)
+#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4)
+#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4)
+
+#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL
+#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL
+
+#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \
+ VTD_DOMAIN_ID_MASK)
+#define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL)
+#define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL)
+#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1)
+
/* Information about page-selective IOTLB invalidate */
struct VTDIOTLBPageInvInfo {
uint16_t domain_id;
--
2.7.4
- [RFC v2 02/22] header update VFIO/IOMMU vSVA APIs against 5.4.0-rc3+, (continued)
- [RFC v2 02/22] header update VFIO/IOMMU vSVA APIs against 5.4.0-rc3+, Liu Yi L, 2019/10/24
- [RFC v2 11/22] intel_iommu: process pasid cache invalidation, Liu Yi L, 2019/10/24
- [RFC v2 12/22] intel_iommu: add present bit check for pasid table entries, Liu Yi L, 2019/10/24
- [RFC v2 14/22] vfio/pci: add iommu_context notifier for pasid bind/unbind, Liu Yi L, 2019/10/24
- [RFC v2 13/22] intel_iommu: add PASID cache management infrastructure, Liu Yi L, 2019/10/24
- [RFC v2 15/22] intel_iommu: bind/unbind guest page table to host, Liu Yi L, 2019/10/24
- [RFC v2 17/22] intel_iommu: replay pasid binds after context cache invalidation, Liu Yi L, 2019/10/24
- [RFC v2 16/22] intel_iommu: replay guest pasid bindings to host, Liu Yi L, 2019/10/24
- [RFC v2 18/22] intel_iommu: do not passdown pasid bind for PASID #0, Liu Yi L, 2019/10/24
- [RFC v2 19/22] vfio/pci: add iommu_context notifier for PASID-based iotlb flush, Liu Yi L, 2019/10/24
- [RFC v2 20/22] intel_iommu: process PASID-based iotlb invalidation,
Liu Yi L <=
- [RFC v2 21/22] intel_iommu: propagate PASID-based iotlb invalidation to host, Liu Yi L, 2019/10/24
- [RFC v2 22/22] intel_iommu: process PASID-based Device-TLB invalidation, Liu Yi L, 2019/10/24
- Re: [RFC v2 00/22] intel_iommu: expose Shared Virtual Addressing to VM, no-reply, 2019/10/25
- Re: [RFC v2 00/22] intel_iommu: expose Shared Virtual Addressing to VM, no-reply, 2019/10/25
- Re: [RFC v2 00/22] intel_iommu: expose Shared Virtual Addressing to VM, Jason Wang, 2019/10/25