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[PULL 06/51] target/arm: Split arm_cpu_data_is_big_endian
From: |
Peter Maydell |
Subject: |
[PULL 06/51] target/arm: Split arm_cpu_data_is_big_endian |
Date: |
Thu, 24 Oct 2019 17:26:39 +0100 |
From: Richard Henderson <address@hidden>
Set TBFLAG_ANY.BE_DATA in rebuild_hflags_common_32 and
rebuild_hflags_a64 instead of rebuild_hflags_common, where we do
not need to re-test is_a64() nor re-compute the various inputs.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 49 +++++++++++++++++++++++++++------------------
target/arm/helper.c | 16 +++++++++++----
2 files changed, 42 insertions(+), 23 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ad79a6153bb..4d961474ce7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3108,33 +3108,44 @@ static inline uint64_t arm_sctlr(CPUARMState *env, int
el)
}
}
+static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
+ bool sctlr_b)
+{
+#ifdef CONFIG_USER_ONLY
+ /*
+ * In system mode, BE32 is modelled in line with the
+ * architecture (as word-invariant big-endianness), where loads
+ * and stores are done little endian but from addresses which
+ * are adjusted by XORing with the appropriate constant. So the
+ * endianness to use for the raw data access is not affected by
+ * SCTLR.B.
+ * In user mode, however, we model BE32 as byte-invariant
+ * big-endianness (because user-only code cannot tell the
+ * difference), and so we need to use a data access endianness
+ * that depends on SCTLR.B.
+ */
+ if (sctlr_b) {
+ return true;
+ }
+#endif
+ /* In 32bit endianness is determined by looking at CPSR's E bit */
+ return env->uncached_cpsr & CPSR_E;
+}
+
+static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
+{
+ return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
+}
/* Return true if the processor is in big-endian mode. */
static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
{
- /* In 32bit endianness is determined by looking at CPSR's E bit */
if (!is_a64(env)) {
- return
-#ifdef CONFIG_USER_ONLY
- /* In system mode, BE32 is modelled in line with the
- * architecture (as word-invariant big-endianness), where loads
- * and stores are done little endian but from addresses which
- * are adjusted by XORing with the appropriate constant. So the
- * endianness to use for the raw data access is not affected by
- * SCTLR.B.
- * In user mode, however, we model BE32 as byte-invariant
- * big-endianness (because user-only code cannot tell the
- * difference), and so we need to use a data access endianness
- * that depends on SCTLR.B.
- */
- arm_sctlr_b(env) ||
-#endif
- ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
+ return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
} else {
int cur_el = arm_current_el(env);
uint64_t sctlr = arm_sctlr(env, cur_el);
-
- return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0;
+ return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
}
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f05d0424745..4c65476d936 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11061,9 +11061,6 @@ static uint32_t rebuild_hflags_common(CPUARMState *env,
int fp_el,
flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX,
arm_to_core_mmu_idx(mmu_idx));
- if (arm_cpu_data_is_big_endian(env)) {
- flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
- }
if (arm_singlestep_active(env)) {
flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1);
}
@@ -11073,7 +11070,14 @@ static uint32_t rebuild_hflags_common(CPUARMState
*env, int fp_el,
static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx, uint32_t flags)
{
- flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
+ bool sctlr_b = arm_sctlr_b(env);
+
+ if (sctlr_b) {
+ flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1);
+ }
+ if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
+ flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
+ }
flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
@@ -11122,6 +11126,10 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env,
int el, int fp_el,
sctlr = arm_sctlr(env, el);
+ if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
+ flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
+ }
+
if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
/*
* In order to save space in flags, we record only whether
--
2.20.1
- [PULL 00/51] target-arm queue, Peter Maydell, 2019/10/24
- [PULL 03/51] target/arm: Split out rebuild_hflags_common, Peter Maydell, 2019/10/24
- [PULL 02/51] aspeed: Add an AST2600 eval board, Peter Maydell, 2019/10/24
- [PULL 01/51] hw/gpio: Fix property accessors of the AST2600 GPIO 1.8V model, Peter Maydell, 2019/10/24
- [PULL 05/51] target/arm: Split out rebuild_hflags_common_32, Peter Maydell, 2019/10/24
- [PULL 04/51] target/arm: Split out rebuild_hflags_a64, Peter Maydell, 2019/10/24
- [PULL 06/51] target/arm: Split arm_cpu_data_is_big_endian,
Peter Maydell <=
- [PULL 08/51] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/24
- [PULL 09/51] target/arm: Split out rebuild_hflags_a32, Peter Maydell, 2019/10/24
- [PULL 11/51] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/24
- [PULL 10/51] target/arm: Split out rebuild_hflags_aprofile, Peter Maydell, 2019/10/24
- [PULL 07/51] target/arm: Split out rebuild_hflags_m32, Peter Maydell, 2019/10/24
- [PULL 14/51] target/arm: Add arm_rebuild_hflags, Peter Maydell, 2019/10/24
- [PULL 15/51] target/arm: Split out arm_mmu_idx_el, Peter Maydell, 2019/10/24
- [PULL 16/51] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/24
- [PULL 12/51] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/24
- [PULL 18/51] target/arm: Rebuild hflags at EL changes, Peter Maydell, 2019/10/24