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[PULL 48/51] hw/arm/bcm2836: Make the SoC code modular
From: |
Peter Maydell |
Subject: |
[PULL 48/51] hw/arm/bcm2836: Make the SoC code modular |
Date: |
Thu, 24 Oct 2019 17:27:21 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
This file creates the BCM2836/BCM2837 blocks.
The biggest differences with the BCM2838 we are going to add, are
the base addresses of the interrupt controller and the peripherals.
Add these addresses in the BCM283XInfo structure to make this
block more modular. Remove the MCORE_OFFSET offset as it is
not useful and rather confusing.
Reviewed-by: Esteban Bosse <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/bcm2836.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 723aef6bf51..019e67b9068 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -16,15 +16,11 @@
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
-/* Peripheral base address seen by the CPU */
-#define BCM2836_PERI_BASE 0x3F000000
-
-/* "QA7" (Pi2) interrupt controller and mailboxes etc. */
-#define BCM2836_CONTROL_BASE 0x40000000
-
struct BCM283XInfo {
const char *name;
const char *cpu_type;
+ hwaddr peri_base; /* Peripheral base address seen by the CPU */
+ hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
};
@@ -32,12 +28,16 @@ static const BCM283XInfo bcm283x_socs[] = {
{
.name = TYPE_BCM2836,
.cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"),
+ .peri_base = 0x3f000000,
+ .ctrl_base = 0x40000000,
.clusterid = 0xf,
},
#ifdef TARGET_AARCH64
{
.name = TYPE_BCM2837,
.cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
+ .peri_base = 0x3f000000,
+ .ctrl_base = 0x40000000,
.clusterid = 0x0,
},
#endif
@@ -104,7 +104,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
- BCM2836_PERI_BASE, 1);
+ info->peri_base, 1);
/* bcm2836 interrupt controller (and mailboxes, etc.) */
object_property_set_bool(OBJECT(&s->control), true, "realized", &err);
@@ -113,7 +113,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, BCM2836_CONTROL_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
@@ -126,7 +126,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
/* set periphbase/CBAR value for CPU-local registers */
object_property_set_int(OBJECT(&s->cpus[n]),
- BCM2836_PERI_BASE + MSYNC_OFFSET,
+ info->peri_base,
"reset-cbar", &err);
if (err) {
error_propagate(errp, err);
--
2.20.1
- [PULL 37/51] target/arm: Allow SVE to be disabled via a CPU property, (continued)
- [PULL 37/51] target/arm: Allow SVE to be disabled via a CPU property, Peter Maydell, 2019/10/24
- [PULL 40/51] target/arm/kvm64: max cpu: Enable SVE when available, Peter Maydell, 2019/10/24
- [PULL 41/51] target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features, Peter Maydell, 2019/10/24
- [PULL 39/51] target/arm/kvm64: Add kvm_arch_get/put_sve, Peter Maydell, 2019/10/24
- [PULL 38/51] target/arm/cpu64: max cpu: Introduce sve<N> properties, Peter Maydell, 2019/10/24
- [PULL 44/51] hw/misc/bcm2835_thermal: Add a dummy BCM2835 thermal sensor, Peter Maydell, 2019/10/24
- [PULL 45/51] hw/arm/bcm2835_peripherals: Use the thermal sensor block, Peter Maydell, 2019/10/24
- [PULL 43/51] target/arm/kvm: host cpu: Add support for sve<N> properties, Peter Maydell, 2019/10/24
- [PULL 47/51] hw/arm/bcm2835_peripherals: Use the SYS_timer, Peter Maydell, 2019/10/24
- [PULL 46/51] hw/timer/bcm2835: Add the BCM2835 SYS_timer, Peter Maydell, 2019/10/24
- [PULL 48/51] hw/arm/bcm2836: Make the SoC code modular,
Peter Maydell <=
- [PULL 42/51] target/arm/cpu64: max cpu: Support sve properties with KVM, Peter Maydell, 2019/10/24
- [PULL 49/51] hw/arm/bcm2836: Rename cpus[] as cpu[].core, Peter Maydell, 2019/10/24
- [PULL 51/51] hw/arm/highbank: Use AddressSpace when using write_secondary_boot(), Peter Maydell, 2019/10/24
- [PULL 50/51] hw/arm/raspi: Use AddressSpace when using arm_boot::write_secondary_boot, Peter Maydell, 2019/10/24
- Re: [PULL 00/51] target-arm queue, Philippe Mathieu-Daudé, 2019/10/24