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RE: [PATCH v5] ssi: xilinx_spips: Skip spi bus update for a few register
From: |
Sai Pavan Boddu |
Subject: |
RE: [PATCH v5] ssi: xilinx_spips: Skip spi bus update for a few register writes |
Date: |
Tue, 29 Oct 2019 10:07:19 +0000 |
Thanks Francisco & Alistair for review.
I have sent V6 with Review tags and commit message fix.
Regards,
Sai Pavan
> -----Original Message-----
> From: Francisco Iglesias <address@hidden>
> Sent: Friday, October 25, 2019 6:47 PM
> To: Sai Pavan Boddu <address@hidden>
> Cc: Alistair Francis <address@hidden>; Peter Maydell
> <address@hidden>; Edgar Iglesias <address@hidden>; qemu-
> address@hidden
> Subject: Re: [PATCH v5] ssi: xilinx_spips: Skip spi bus update for a few
> register
> writes
>
> Hi Sai,
>
> On [2019 Oct 25] Fri 11:02:11, Sai Pavan Boddu wrote:
> > A few configuration register writes need not update the spi bus state,
> > so just return after register write.
>
> s/register write/the register write/
>
> >
> > Signed-off-by: Sai Pavan Boddu <address@hidden>
>
> After above change:
>
> Reviewed-by: Francisco Iglesias <address@hidden>
> Tested-by: Francisco Iglesias <address@hidden>
>
> Best regards,
> Francisco Iglesias
>
> > ---
> >
> > Changes for V2:
> > Just skip update of spips cs and fifos
> > Update commit message accordingly
> > Changes for V4:
> > Avoid checking for zynqmp qspi
> > Skip spi bus update for few of the registers Changes for V4:
> > Move the register list to existing switch case above.
> > Change for V5:
> > Fixed Commit message.
> >
> > hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++----
> > 1 file changed, 18 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index
> > a309c71..0d6c2e1 100644
> > --- a/hw/ssi/xilinx_spips.c
> > +++ b/hw/ssi/xilinx_spips.c
> > @@ -109,6 +109,7 @@
> > #define R_GPIO (0x30 / 4)
> > #define R_LPBK_DLY_ADJ (0x38 / 4)
> > #define R_LPBK_DLY_ADJ_RESET (0x33)
> > +#define R_IOU_TAPDLY_BYPASS (0x3C / 4)
> > #define R_TXD1 (0x80 / 4)
> > #define R_TXD2 (0x84 / 4)
> > #define R_TXD3 (0x88 / 4)
> > @@ -139,6 +140,8 @@
> > #define R_LQSPI_STS (0xA4 / 4)
> > #define LQSPI_STS_WR_RECVD (1 << 1)
> >
> > +#define R_DUMMY_CYCLE_EN (0xC8 / 4)
> > +#define R_ECO (0xF8 / 4)
> > #define R_MOD_ID (0xFC / 4)
> >
> > #define R_GQSPI_SELECT (0x144 / 4)
> > @@ -970,6 +973,7 @@ static void xilinx_spips_write(void *opaque,
> > hwaddr addr, {
> > int mask = ~0;
> > XilinxSPIPS *s = opaque;
> > + bool try_flush = true;
> >
> > DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr,
> (unsigned)value);
> > addr >>= 2;
> > @@ -1019,13 +1023,23 @@ static void xilinx_spips_write(void *opaque,
> hwaddr addr,
> > tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
> > s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
> > goto no_reg_update;
> > + /* Skip SPI bus update for below registers writes */
> > + case R_GPIO:
> > + case R_LPBK_DLY_ADJ:
> > + case R_IOU_TAPDLY_BYPASS:
> > + case R_DUMMY_CYCLE_EN:
> > + case R_ECO:
> > + try_flush = false;
> > + break;
> > }
> > s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
> > no_reg_update:
> > - xilinx_spips_update_cs_lines(s);
> > - xilinx_spips_check_flush(s);
> > - xilinx_spips_update_cs_lines(s);
> > - xilinx_spips_update_ixr(s);
> > + if (try_flush) {
> > + xilinx_spips_update_cs_lines(s);
> > + xilinx_spips_check_flush(s);
> > + xilinx_spips_update_cs_lines(s);
> > + xilinx_spips_update_ixr(s);
> > + }
> > }
> >
> > static const MemoryRegionOps spips_ops = {
> > --
> > 2.7.4
> >