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[PATCH v15 11/12] hmat acpi: Build Memory Side Cache Information Structu
From: |
Tao Xu |
Subject: |
[PATCH v15 11/12] hmat acpi: Build Memory Side Cache Information Structure(s) |
Date: |
Thu, 7 Nov 2019 15:45:10 +0800 |
From: Liu Jingqi <address@hidden>
This structure describes memory side cache information for memory
proximity domains if the memory side cache is present and the
physical device forms the memory side cache.
The software could use this information to effectively place
the data in memory to maximize the performance of the system
memory that use the memory side cache.
Reviewed-by: Daniel Black <address@hidden>
Reviewed-by: Jonathan Cameron <address@hidden>
Signed-off-by: Liu Jingqi <address@hidden>
Signed-off-by: Tao Xu <address@hidden>
---
No changes in v15.
Changes in v13:
- rename level as cache_level
---
hw/acpi/hmat.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
index 6ec1310e62..931aa60678 100644
--- a/hw/acpi/hmat.c
+++ b/hw/acpi/hmat.c
@@ -135,14 +135,63 @@ static void build_hmat_lb(GArray *table_data,
HMAT_LB_Info *hmat_lb,
}
}
+/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-147 */
+static void build_hmat_cache(GArray *table_data, HMAT_Cache_Info *hmat_cache)
+{
+ /*
+ * Cache Attributes: Bits [3:0] – Total Cache Levels
+ * for this Memory Proximity Domain
+ */
+ uint32_t cache_attr = hmat_cache->total_levels & 0xF;
+
+ /* Bits [7:4] : Cache Level described in this structure */
+ cache_attr |= (hmat_cache->level & 0xF) << 4;
+
+ /* Bits [11:8] - Cache Associativity */
+ cache_attr |= (hmat_cache->associativity & 0x7) << 8;
+
+ /* Bits [15:12] - Write Policy */
+ cache_attr |= (hmat_cache->write_policy & 0x7) << 12;
+
+ /* Bits [31:16] - Cache Line size in bytes */
+ cache_attr |= (hmat_cache->line_size & 0xFFFF) << 16;
+
+ cache_attr = cpu_to_le32(cache_attr);
+
+ /* Type */
+ build_append_int_noprefix(table_data, 2, 2);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Length */
+ build_append_int_noprefix(table_data, 32, 4);
+ /* Proximity Domain for the Memory */
+ build_append_int_noprefix(table_data, hmat_cache->proximity, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
+ /* Memory Side Cache Size */
+ build_append_int_noprefix(table_data, hmat_cache->size, 8);
+ /* Cache Attributes */
+ build_append_int_noprefix(table_data, cache_attr, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /*
+ * Number of SMBIOS handles (n)
+ * Linux kernel uses Memory Side Cache Information Structure
+ * without SMBIOS entries for now, so set Number of SMBIOS handles
+ * as 0.
+ */
+ build_append_int_noprefix(table_data, 0, 2);
+}
+
/* Build HMAT sub table structures */
static void hmat_build_table_structs(GArray *table_data, NumaState *numa_state)
{
uint16_t flags;
uint32_t num_initiator = 0;
uint32_t initiator_list[MAX_NODES];
- int i, hierarchy, type;
+ int i, hierarchy, type, cache_level, total_levels;
HMAT_LB_Info *hmat_lb;
+ HMAT_Cache_Info *hmat_cache;
for (i = 0; i < numa_state->num_nodes; i++) {
flags = 0;
@@ -176,6 +225,27 @@ static void hmat_build_table_structs(GArray *table_data,
NumaState *numa_state)
}
}
}
+
+ /*
+ * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure:
+ * Table 5-147
+ */
+ for (i = 0; i < numa_state->num_nodes; i++) {
+ total_levels = 0;
+ for (cache_level = 1; cache_level <= MAX_HMAT_CACHE_LEVEL;
+ cache_level++) {
+ if (numa_state->hmat_cache[i][cache_level]) {
+ total_levels++;
+ }
+ }
+ for (cache_level = 0; cache_level <= total_levels; cache_level++) {
+ hmat_cache = numa_state->hmat_cache[i][cache_level];
+ if (hmat_cache) {
+ hmat_cache->total_levels = total_levels;
+ build_hmat_cache(table_data, hmat_cache);
+ }
+ }
+ }
}
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state)
--
2.20.1
- Re: [PATCH v15 07/12] numa: Calculate hmat latency and bandwidth entry list, (continued)
- [PATCH v15 06/12] numa: Extend CLI to provide memory latency and bandwidth information, Tao Xu, 2019/11/07
- [PATCH v15 08/12] numa: Extend CLI to provide memory side cache information, Tao Xu, 2019/11/07
- [PATCH v15 10/12] hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s), Tao Xu, 2019/11/07
- [PATCH v15 09/12] hmat acpi: Build Memory Proximity Domain Attributes Structure(s), Tao Xu, 2019/11/07
- [PATCH v15 11/12] hmat acpi: Build Memory Side Cache Information Structure(s),
Tao Xu <=
- [PATCH v15 12/12] tests/bios-tables-test: add test cases for ACPI HMAT, Tao Xu, 2019/11/07
- Re: [PATCH v15 00/12] Build ACPI Heterogeneous Memory Attribute Table (HMAT), Michael S. Tsirkin, 2019/11/07