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[PATCH 0/3] target/arm: More HCR_EL2.TIDx fixes
From: |
Marc Zyngier |
Subject: |
[PATCH 0/3] target/arm: More HCR_EL2.TIDx fixes |
Date: |
Thu, 28 Nov 2019 16:17:15 +0000 |
I started looking the rest of the missing TIDx handling,
and this resulted in the following patches.
There is still one thing I'm a bit puzzled by though:
HCR_EL2.TID0 mandates trapping of the AArch32 JIDR
register, but I couldn't find a trace of it in the QEMU
code, and trying to read it seems to generate an exception.
It isn't like anyone is going to miss it, but I wonder if
it should be implemented... It could also be that I'm missing
the obvious and that my testing is broken! ;-)
Marc Zyngier (3):
target/arm: Honor HCR_EL2.TID2 trapping requirements
target/arm: Honor HCR_EL2.TID1 trapping requirements
target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
target/arm/helper-a64.h | 2 ++
target/arm/helper.c | 64 ++++++++++++++++++++++++++++++----
target/arm/internals.h | 8 +++++
target/arm/translate-vfp.inc.c | 12 +++++--
target/arm/vfp_helper.c | 27 ++++++++++++++
5 files changed, 103 insertions(+), 10 deletions(-)
--
2.20.1
- [PATCH 0/3] target/arm: More HCR_EL2.TIDx fixes,
Marc Zyngier <=
[PATCH 2/3] target/arm: Honor HCR_EL2.TID1 trapping requirements, Marc Zyngier, 2019/11/28