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[PATCH v2 00/14] gdbstub refactor and SVE support
From: |
Alex Bennée |
Subject: |
[PATCH v2 00/14] gdbstub refactor and SVE support |
Date: |
Sat, 30 Nov 2019 08:45:48 +0000 |
Hi,
So this is the first fully working version of the SVE gdbstub
implementation. As before the first set of patches are mostly
re-factoring of the gdbstub register interface. I include a new patch
to default the SVE size to a more reasonable number for linux-user to
mirror what the Linux kernel actually does. Finally the XML that QEMU
generates is closer to that of GDB in terms of the nesting of the
union and keeping all registers intact. If you enable the maximum VQ
you still end up with pages of text if you examine the vector
registers.
Finally I've added a bit more test harness for running gdbstub tests
and included a basic smoke test for SVE itself. It's still not plumbed
into the main test harness yet though as there are complications
caused by the available version of gdb. However I hope I can hide
these in the run-test.py script later and just skip tests that we know
won't work.
Alex Bennée (14):
gdbstub: make GDBState static and have common init function
gdbstub: stop passing GDBState * around and use global
gdbstub: move str_buf to GDBState and use GString
gdbstub: move mem_buf to GDBState and use GByteArray
gdbstub: add helper for 128 bit registers
target/arm: use gdb_get_reg helpers
target/m68k: use gdb_get_reg helpers
gdbstub: extend GByteArray to read register helpers
target/arm: prepare for multiple dynamic XMLs
target/arm: explicitly encode regnum in our XML
target/arm: default SVE length to 64 bytes for linux-user
target/arm: generate xml description of our SVE registers
tests/guest-debug: add a simple test runner
tests/tcg: add a gdbstub testcase for SVE registers
include/exec/gdbstub.h | 49 +-
include/hw/core/cpu.h | 2 +-
target/alpha/cpu.h | 2 +-
target/arm/cpu.h | 34 +-
target/cris/cpu.h | 4 +-
target/hppa/cpu.h | 2 +-
target/i386/cpu.h | 2 +-
target/lm32/cpu.h | 2 +-
target/m68k/cpu.h | 2 +-
target/microblaze/cpu.h | 2 +-
target/mips/internal.h | 2 +-
target/openrisc/cpu.h | 2 +-
target/ppc/cpu.h | 4 +-
target/riscv/cpu.h | 2 +-
target/s390x/internal.h | 2 +-
target/sh4/cpu.h | 2 +-
target/sparc/cpu.h | 2 +-
target/xtensa/cpu.h | 2 +-
gdbstub.c | 892 +++++++++++++-------------
hw/core/cpu.c | 2 +-
target/alpha/gdbstub.c | 2 +-
target/arm/cpu64.c | 3 +
target/arm/gdbstub.c | 169 ++++-
target/arm/gdbstub64.c | 2 +-
target/arm/helper.c | 151 ++++-
target/cris/gdbstub.c | 4 +-
target/hppa/gdbstub.c | 2 +-
target/i386/gdbstub.c | 2 +-
target/lm32/gdbstub.c | 2 +-
target/m68k/gdbstub.c | 2 +-
target/m68k/helper.c | 33 +-
target/microblaze/gdbstub.c | 2 +-
target/mips/gdbstub.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/gdbstub.c | 2 +-
target/ppc/gdbstub.c | 48 +-
target/ppc/translate_init.inc.c | 54 +-
target/riscv/gdbstub.c | 18 +-
target/s390x/gdbstub.c | 30 +-
target/sh4/gdbstub.c | 2 +-
target/sparc/gdbstub.c | 2 +-
target/xtensa/gdbstub.c | 2 +-
tests/.gitignore | 1 +
tests/guest-debug/run-test.py | 57 ++
tests/tcg/aarch64/gdbstub/test-sve.py | 75 +++
45 files changed, 1038 insertions(+), 644 deletions(-)
create mode 100755 tests/guest-debug/run-test.py
create mode 100644 tests/tcg/aarch64/gdbstub/test-sve.py
--
2.20.1
- [PATCH v2 00/14] gdbstub refactor and SVE support,
Alex Bennée <=
- [PATCH v2 04/14] gdbstub: move mem_buf to GDBState and use GByteArray, Alex Bennée, 2019/11/30
- [PATCH v2 01/14] gdbstub: make GDBState static and have common init function, Alex Bennée, 2019/11/30
- [PATCH v2 05/14] gdbstub: add helper for 128 bit registers, Alex Bennée, 2019/11/30
- [PATCH v2 03/14] gdbstub: move str_buf to GDBState and use GString, Alex Bennée, 2019/11/30
- [PATCH v2 06/14] target/arm: use gdb_get_reg helpers, Alex Bennée, 2019/11/30
- [PATCH v2 07/14] target/m68k: use gdb_get_reg helpers, Alex Bennée, 2019/11/30
- [PATCH v2 10/14] target/arm: explicitly encode regnum in our XML, Alex Bennée, 2019/11/30
- [PATCH v2 09/14] target/arm: prepare for multiple dynamic XMLs, Alex Bennée, 2019/11/30
- [PATCH v2 12/14] target/arm: generate xml description of our SVE registers, Alex Bennée, 2019/11/30