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[PATCH 04/11] target/arm: Reduce CPSR_RESERVED
From: |
Richard Henderson |
Subject: |
[PATCH 04/11] target/arm: Reduce CPSR_RESERVED |
Date: |
Tue, 3 Dec 2019 14:53:26 -0800 |
Since v8.0, the CPSR_RESERVED bits have been allocated.
We are not yet implementing ARMv8.4-DIT; retain CPSR_RESERVED,
since that overlaps with our current hack for AA32 single step.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 22c5706835..49dc436e5e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1149,12 +1149,16 @@ void pmu_init(ARMCPU *cpu);
#define CPSR_IT_2_7 (0xfc00U)
#define CPSR_GE (0xfU << 16)
#define CPSR_IL (1U << 20)
-/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
+/*
+ * Note that the RESERVED bits include bit 21, which is PSTATE_SS in
* an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
* env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
* where it is live state but not accessible to the AArch32 code.
+ *
+ * TODO: With ARMv8.4-DIT, bit 21 is DIT in AArch32 (bit 24 for AArch64).
+ * We will need to move AArch32 SS somewhere else at that point.
*/
-#define CPSR_RESERVED (0x7U << 21)
+#define CPSR_RESERVED (1U << 21)
#define CPSR_J (1U << 24)
#define CPSR_IT_0_1 (3U << 25)
#define CPSR_Q (1U << 27)
--
2.17.1
- [PATCH 00/11] target/arm: Implement ARMv8.1-PAN + ARMv8.2-ATS1E1, Richard Henderson, 2019/12/03
- [PATCH 02/11] target/arm: Add arm_mmu_idx_is_stage1, Richard Henderson, 2019/12/03
- [PATCH 01/11] cputlb: Handle NB_MMU_MODES > TARGET_PAGE_BITS_MIN, Richard Henderson, 2019/12/03
- [PATCH 04/11] target/arm: Reduce CPSR_RESERVED,
Richard Henderson <=
- [PATCH 06/11] target/arm: Update MSR access for PAN, Richard Henderson, 2019/12/03
- [PATCH 07/11] target/arm: Update arm_mmu_idx_el for PAN, Richard Henderson, 2019/12/03
- [PATCH 05/11] target/arm: Add isar_feature tests for PAN + ATS1E1, Richard Henderson, 2019/12/03
- [PATCH 03/11] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled, Richard Henderson, 2019/12/03
- [PATCH 09/11] target/arm: Set PAN bit as required on exception entry, Richard Henderson, 2019/12/03