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Re: [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 tra
From: |
Peter Maydell |
Subject: |
Re: [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime |
Date: |
Fri, 6 Dec 2019 17:05:49 +0000 |
On Tue, 3 Dec 2019 at 02:30, Richard Henderson
<address@hidden> wrote:
>
> Since we only support a single ASID, flush the tlb when it changes.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/helper.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 9df55a8d6b..2a4d4c2c0d 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3740,6 +3740,15 @@ static void vmsa_ttbr_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + /*
> + * If we are running with E2&0 regime, then the ASID is active.
> + * Flush if that changes.
> + */
> + if ((arm_hcr_el2_eff(env) & HCR_E2H) &&
> + extract64(raw_read(env, ri) ^ value, 48, 16)) {
> + tlb_flush_by_mmuidx(env_cpu(env),
> + ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0);
> + }
> raw_write(env, ri, value);
> }
For the existing EL1 setup we have separate write functions
for TTBR registers and for TCR_EL1 (vmsa_tcr_el1_write()
and vmsa_ttbr_write()), rather than a single one, and they
don't do the same thing. Why do we use a single writefn
here? It looks particularly odd because we're actually looking
at the value written here.
thanks
-- PMM
- Re: [PATCH v4 23/40] target/arm: Update ctr_el0_access for EL2, (continued)
- [PATCH v4 15/40] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, Richard Henderson, 2019/12/02
- [PATCH v4 17/40] target/arm: Tidy ARMMMUIdx m-profile definitions, Richard Henderson, 2019/12/02
- [PATCH v4 19/40] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/12/02
- [PATCH v4 22/40] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2019/12/02
- [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2019/12/02
- Re: [PATCH v4 29/40] target/arm: Flush tlb for ASID changes in EL2&0 translation regime,
Peter Maydell <=
- [PATCH v4 24/40] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2019/12/02
- [PATCH v4 30/40] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2019/12/02
- [PATCH v4 36/40] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2019/12/02
- [PATCH v4 27/40] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2019/12/02