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[PULL v2 16/27] hmat acpi: Build Memory Side Cache Information Structure
From: |
Michael S. Tsirkin |
Subject: |
[PULL v2 16/27] hmat acpi: Build Memory Side Cache Information Structure(s) |
Date: |
Mon, 23 Dec 2019 11:42:09 -0500 |
From: Liu Jingqi <address@hidden>
This structure describes memory side cache information for memory
proximity domains if the memory side cache is present and the
physical device forms the memory side cache.
The software could use this information to effectively place
the data in memory to maximize the performance of the system
memory that use the memory side cache.
Acked-by: Markus Armbruster <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Reviewed-by: Daniel Black <address@hidden>
Reviewed-by: Jonathan Cameron <address@hidden>
Signed-off-by: Liu Jingqi <address@hidden>
Signed-off-by: Tao Xu <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/acpi/hmat.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 68 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
index 4635d45dee..7c24bb5371 100644
--- a/hw/acpi/hmat.c
+++ b/hw/acpi/hmat.c
@@ -143,14 +143,62 @@ static void build_hmat_lb(GArray *table_data,
HMAT_LB_Info *hmat_lb,
g_free(entry_list);
}
+/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-147 */
+static void build_hmat_cache(GArray *table_data, uint8_t total_levels,
+ NumaHmatCacheOptions *hmat_cache)
+{
+ /*
+ * Cache Attributes: Bits [3:0] – Total Cache Levels
+ * for this Memory Proximity Domain
+ */
+ uint32_t cache_attr = total_levels;
+
+ /* Bits [7:4] : Cache Level described in this structure */
+ cache_attr |= (uint32_t) hmat_cache->level << 4;
+
+ /* Bits [11:8] - Cache Associativity */
+ cache_attr |= (uint32_t) hmat_cache->associativity << 8;
+
+ /* Bits [15:12] - Write Policy */
+ cache_attr |= (uint32_t) hmat_cache->policy << 12;
+
+ /* Bits [31:16] - Cache Line size in bytes */
+ cache_attr |= (uint32_t) hmat_cache->line << 16;
+
+ /* Type */
+ build_append_int_noprefix(table_data, 2, 2);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Length */
+ build_append_int_noprefix(table_data, 32, 4);
+ /* Proximity Domain for the Memory */
+ build_append_int_noprefix(table_data, hmat_cache->node_id, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
+ /* Memory Side Cache Size */
+ build_append_int_noprefix(table_data, hmat_cache->size, 8);
+ /* Cache Attributes */
+ build_append_int_noprefix(table_data, cache_attr, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /*
+ * Number of SMBIOS handles (n)
+ * Linux kernel uses Memory Side Cache Information Structure
+ * without SMBIOS entries for now, so set Number of SMBIOS handles
+ * as 0.
+ */
+ build_append_int_noprefix(table_data, 0, 2);
+}
+
/* Build HMAT sub table structures */
static void hmat_build_table_structs(GArray *table_data, NumaState *numa_state)
{
uint16_t flags;
uint32_t num_initiator = 0;
uint32_t initiator_list[MAX_NODES];
- int i, hierarchy, type;
+ int i, hierarchy, type, cache_level, total_levels;
HMAT_LB_Info *hmat_lb;
+ NumaHmatCacheOptions *hmat_cache;
for (i = 0; i < numa_state->num_nodes; i++) {
flags = 0;
@@ -184,6 +232,25 @@ static void hmat_build_table_structs(GArray *table_data,
NumaState *numa_state)
}
}
}
+
+ /*
+ * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure:
+ * Table 5-147
+ */
+ for (i = 0; i < numa_state->num_nodes; i++) {
+ total_levels = 0;
+ for (cache_level = 1; cache_level < HMAT_LB_LEVELS; cache_level++) {
+ if (numa_state->hmat_cache[i][cache_level]) {
+ total_levels++;
+ }
+ }
+ for (cache_level = 0; cache_level <= total_levels; cache_level++) {
+ hmat_cache = numa_state->hmat_cache[i][cache_level];
+ if (hmat_cache) {
+ build_hmat_cache(table_data, total_levels, hmat_cache);
+ }
+ }
+ }
}
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state)
--
MST
- [PULL v2 06/27] intel_iommu: fix bug to read DMAR_RTADDR_REG, (continued)
- [PULL v2 06/27] intel_iommu: fix bug to read DMAR_RTADDR_REG, Michael S. Tsirkin, 2019/12/23
- [PULL v2 07/27] virtio: update queue size on guest write, Michael S. Tsirkin, 2019/12/23
- [PULL v2 09/27] Implement backend program convention command for vhost-user-blk, Michael S. Tsirkin, 2019/12/23
- [PULL v2 08/27] virtio-pci: disable vring processing when bus-mastering is disabled, Michael S. Tsirkin, 2019/12/23
- [PULL v2 10/27] virtio: don't enable notifications during polling, Michael S. Tsirkin, 2019/12/23
- [PULL v2 11/27] numa: Extend CLI to provide initiator information for numa nodes, Michael S. Tsirkin, 2019/12/23
- [PULL v2 12/27] numa: Extend CLI to provide memory latency and bandwidth information, Michael S. Tsirkin, 2019/12/23
- [PULL v2 13/27] numa: Extend CLI to provide memory side cache information, Michael S. Tsirkin, 2019/12/23
- [PULL v2 14/27] hmat acpi: Build Memory Proximity Domain Attributes Structure(s), Michael S. Tsirkin, 2019/12/23
- [PULL v2 15/27] hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s), Michael S. Tsirkin, 2019/12/23
- [PULL v2 16/27] hmat acpi: Build Memory Side Cache Information Structure(s),
Michael S. Tsirkin <=
- [PULL v2 17/27] tests/numa: Add case for QMP build HMAT, Michael S. Tsirkin, 2019/12/23
- [PULL v2 18/27] tests/bios-tables-test: add test cases for ACPI HMAT, Michael S. Tsirkin, 2019/12/23
- [PULL v2 20/27] virtio-mmio: Clear v2 transport state on soft reset, Michael S. Tsirkin, 2019/12/23
- [PULL v2 19/27] ACPI: add expected files for HMAT tests (acpihmat), Michael S. Tsirkin, 2019/12/23
- [PULL v2 21/27] hw/pci/pci_host: Remove redundant PCI_DPRINTF(), Michael S. Tsirkin, 2019/12/23
- [PULL v2 22/27] hw/pci/pci_host: Let pci_data_[read/write] use unsigned 'size' argument, Michael S. Tsirkin, 2019/12/23
- [PULL v2 23/27] vhost-user: add VHOST_USER_RESET_DEVICE to reset devices, Michael S. Tsirkin, 2019/12/23
- [PULL v2 24/27] vhost-user-scsi: reset the device if supported, Michael S. Tsirkin, 2019/12/23
- [PULL v2 25/27] hw: fix using 4.2 compat in 5.0 machine types for i440fx/q35, Michael S. Tsirkin, 2019/12/23
- [PULL v2 26/27] virtio: make seg_max virtqueue size dependent, Michael S. Tsirkin, 2019/12/23