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[PULL 12/12] accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_han
From: |
Richard Henderson |
Subject: |
[PULL 12/12] accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler |
Date: |
Tue, 2 Jun 2020 10:01:51 -0700 |
From: Nick Hudson <skrll@netbsd.org>
Fix qemu build on NetBSD/evbarm-aarch64 by providing a NetBSD specific
cpu_signal_handler.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nick Hudson <skrll@netbsd.org>
Message-Id: <20200517101529.5367-1-skrll@netbsd.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/user-exec.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index bc391eb454..d8b027f8c1 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -558,6 +558,32 @@ int cpu_signal_handler(int host_signum, void *pinfo,
#elif defined(__aarch64__)
+#if defined(__NetBSD__)
+
+#include <ucontext.h>
+#include <sys/siginfo.h>
+
+int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
+{
+ ucontext_t *uc = puc;
+ siginfo_t *si = pinfo;
+ unsigned long pc;
+ int is_write;
+ uint32_t esr;
+
+ pc = uc->uc_mcontext.__gregs[_REG_PC];
+ esr = si->si_trap;
+
+ /*
+ * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC
+ * is 0b10010x: then bit 6 is the WnR bit
+ */
+ is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
+ return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask);
+}
+
+#else
+
#ifndef ESR_MAGIC
/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
#define ESR_MAGIC 0x45535201
@@ -620,6 +646,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, void
*puc)
}
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
}
+#endif
#elif defined(__s390__)
--
2.25.1
- [PULL 02/12] tcg: Implement gvec support for rotate by vector, (continued)
- [PULL 02/12] tcg: Implement gvec support for rotate by vector, Richard Henderson, 2020/06/02
- [PULL 03/12] tcg: Remove expansion to shift by vector from do_shifts, Richard Henderson, 2020/06/02
- [PULL 04/12] tcg: Implement gvec support for rotate by scalar, Richard Henderson, 2020/06/02
- [PULL 05/12] tcg/i386: Implement INDEX_op_rotl{i,s,v}_vec, Richard Henderson, 2020/06/02
- [PULL 06/12] tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec, Richard Henderson, 2020/06/02
- [PULL 07/12] tcg/ppc: Implement INDEX_op_rot[lr]v_vec, Richard Henderson, 2020/06/02
- [PULL 08/12] target/ppc: Use tcg_gen_gvec_rotlv, Richard Henderson, 2020/06/02
- [PULL 10/12] tcg: Improve move ops in liveness_pass_2, Richard Henderson, 2020/06/02
- [PULL 11/12] accel/tcg: Adjust cpu_signal_handler for NetBSD/arm, Richard Henderson, 2020/06/02
- [PULL 09/12] target/s390x: Use tcg_gen_gvec_rotl{i,s,v}, Richard Henderson, 2020/06/02
- [PULL 12/12] accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler,
Richard Henderson <=
- Re: [PULL 00/12] tcg patch queue, Peter Maydell, 2020/06/02