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[PATCH v7 17/22] hw/block/nvme: factor out pmr setup
From: |
Klaus Jensen |
Subject: |
[PATCH v7 17/22] hw/block/nvme: factor out pmr setup |
Date: |
Tue, 9 Jun 2020 21:03:28 +0200 |
From: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20200514044611.734782-19-its@irrelevant.dk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
---
hw/block/nvme.c | 95 ++++++++++++++++++++++++++-----------------------
1 file changed, 51 insertions(+), 44 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 8aabb4c3c39f..b954e7b7b2fe 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -57,6 +57,7 @@
#define NVME_REG_SIZE 0x1000
#define NVME_DB_SIZE 4
#define NVME_CMB_BIR 2
+#define NVME_PMR_BIR 2
#define NVME_GUEST_ERR(trace, fmt, ...) \
do { \
@@ -1461,6 +1462,55 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice
*pci_dev)
PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
}
+static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
+{
+ /* Controller Capabilities register */
+ NVME_CAP_SET_PMRS(n->bar.cap, 1);
+
+ /* PMR Capabities register */
+ n->bar.pmrcap = 0;
+ NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
+ NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
+ NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
+ NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
+ /* Turn on bit 1 support */
+ NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
+ NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
+ NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
+
+ /* PMR Control register */
+ n->bar.pmrctl = 0;
+ NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
+
+ /* PMR Status register */
+ n->bar.pmrsts = 0;
+ NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
+ NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
+ NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
+ NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
+
+ /* PMR Elasticity Buffer Size register */
+ n->bar.pmrebs = 0;
+ NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
+ NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
+ NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
+
+ /* PMR Sustained Write Throughput register */
+ n->bar.pmrswtp = 0;
+ NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
+ NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
+
+ /* PMR Memory Space Control register */
+ n->bar.pmrmsc = 0;
+ NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
+ NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
+
+ pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
+ PCI_BASE_ADDRESS_SPACE_MEMORY |
+ PCI_BASE_ADDRESS_MEM_TYPE_64 |
+ PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
+}
+
static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev)
{
uint8_t *pci_conf = pci_dev->config;
@@ -1539,50 +1589,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error
**errp)
if (n->params.cmb_size_mb) {
nvme_init_cmb(n, pci_dev);
} else if (n->pmrdev) {
- /* Controller Capabilities register */
- NVME_CAP_SET_PMRS(n->bar.cap, 1);
-
- /* PMR Capabities register */
- n->bar.pmrcap = 0;
- NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
- NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
- NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2);
- NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
- /* Turn on bit 1 support */
- NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
- NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
- NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
-
- /* PMR Control register */
- n->bar.pmrctl = 0;
- NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
-
- /* PMR Status register */
- n->bar.pmrsts = 0;
- NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
- NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
- NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
- NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
-
- /* PMR Elasticity Buffer Size register */
- n->bar.pmrebs = 0;
- NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
- NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
- NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
-
- /* PMR Sustained Write Throughput register */
- n->bar.pmrswtp = 0;
- NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
- NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
-
- /* PMR Memory Space Control register */
- n->bar.pmrmsc = 0;
- NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
- NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
-
- pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
- PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
- PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
+ nvme_init_pmr(n, pci_dev);
}
for (i = 0; i < n->num_namespaces; i++) {
--
2.27.0
- [PATCH v7 07/22] hw/block/nvme: fix pin-based interrupt behavior, (continued)
- [PATCH v7 07/22] hw/block/nvme: fix pin-based interrupt behavior, Klaus Jensen, 2020/06/09
- [PATCH v7 03/22] hw/block/nvme: remove superfluous breaks, Klaus Jensen, 2020/06/09
- [PATCH v7 05/22] hw/block/nvme: use constants in identify, Klaus Jensen, 2020/06/09
- [PATCH v7 06/22] hw/block/nvme: refactor nvme_addr_read, Klaus Jensen, 2020/06/09
- [PATCH v7 13/22] hw/block/nvme: add namespace helpers, Klaus Jensen, 2020/06/09
- [PATCH v7 10/22] hw/block/nvme: factor out property/constraint checks, Klaus Jensen, 2020/06/09
- [PATCH v7 11/22] hw/block/nvme: factor out device state setup, Klaus Jensen, 2020/06/09
- [PATCH v7 16/22] hw/block/nvme: factor out cmb setup, Klaus Jensen, 2020/06/09
- [PATCH v7 15/22] hw/block/nvme: factor out pci setup, Klaus Jensen, 2020/06/09
- [PATCH v7 14/22] hw/block/nvme: factor out namespace setup, Klaus Jensen, 2020/06/09
- [PATCH v7 17/22] hw/block/nvme: factor out pmr setup,
Klaus Jensen <=
- [PATCH v7 19/22] hw/block/nvme: factor out controller identify setup, Klaus Jensen, 2020/06/09
- [PATCH v7 21/22] hw/block/nvme: add msix_qsize parameter, Klaus Jensen, 2020/06/09
- [PATCH v7 12/22] hw/block/nvme: factor out block backend setup, Klaus Jensen, 2020/06/09
- [PATCH v7 20/22] hw/block/nvme: Verify msix_vector_use() returned value, Klaus Jensen, 2020/06/09
- [PATCH v7 18/22] hw/block/nvme: do cmb/pmr init as part of pci init, Klaus Jensen, 2020/06/09
- [PATCH v7 22/22] hw/block/nvme: verify msix_init_exclusive_bar() return value, Klaus Jensen, 2020/06/09
- Re: [PATCH v7 00/22] nvme: small fixes, refactoring and cleanups, Kevin Wolf, 2020/06/15