[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 11/23] target/arm: Convert Neon 2-reg-scalar float multiplies to d
From: |
Peter Maydell |
Subject: |
[PULL 11/23] target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree |
Date: |
Tue, 16 Jun 2020 10:56:50 +0100 |
Convert the float versions of VMLA, VMLS and VMUL in the Neon
2-reg-scalar group to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
As noted in the comment on the WRAP_FP_FN macro, we could have
had a do_2scalar_fp() function, but for 3 insns it seemed
simpler to just do the wrapping to get hold of the fpstatus ptr.
(These are the only fp insns in the group.)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/neon-dp.decode | 3 ++
target/arm/translate-neon.inc.c | 65 +++++++++++++++++++++++++++++++++
target/arm/translate.c | 37 ++-----------------
3 files changed, 71 insertions(+), 34 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index 983747b785f..cc2ee9641d6 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -478,9 +478,12 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 .
op:1 1 .... @1reg_imm
&2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp
VMLA_2sc 1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar
+ VMLA_F_2sc 1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar
VMLS_2sc 1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar
+ VMLS_F_2sc 1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar
VMUL_2sc 1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar
+ VMUL_F_2sc 1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar
]
}
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index 478a0dd5c1d..a5c7d60bdac 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -2481,3 +2481,68 @@ static bool trans_VMLS_2sc(DisasContext *s, arg_2scalar
*a)
return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
}
+
+/*
+ * Rather than have a float-specific version of do_2scalar just for
+ * three insns, we wrap a NeonGenTwoSingleOpFn to turn it into
+ * a NeonGenTwoOpFn.
+ */
+#define WRAP_FP_FN(WRAPNAME, FUNC) \
+ static void WRAPNAME(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm) \
+ { \
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1); \
+ FUNC(rd, rn, rm, fpstatus); \
+ tcg_temp_free_ptr(fpstatus); \
+ }
+
+WRAP_FP_FN(gen_VMUL_F_mul, gen_helper_vfp_muls)
+WRAP_FP_FN(gen_VMUL_F_add, gen_helper_vfp_adds)
+WRAP_FP_FN(gen_VMUL_F_sub, gen_helper_vfp_subs)
+
+static bool trans_VMUL_F_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_mul,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], NULL);
+}
+
+static bool trans_VMLA_F_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_mul,
+ NULL,
+ };
+ static NeonGenTwoOpFn * const accfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_add,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
+}
+
+static bool trans_VMLS_F_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_mul,
+ NULL,
+ };
+ static NeonGenTwoOpFn * const accfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_sub,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e9cc237ef80..e4a6a38c782 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5187,15 +5187,11 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
case 0: /* Integer VMLA scalar */
case 4: /* Integer VMLS scalar */
case 8: /* Integer VMUL scalar */
- return 1; /* handled by decodetree */
-
case 1: /* Float VMLA scalar */
case 5: /* Floating point VMLS scalar */
case 9: /* Floating point VMUL scalar */
- if (size == 1) {
- return 1;
- }
- /* fall through */
+ return 1; /* handled by decodetree */
+
case 12: /* VQDMULH scalar */
case 13: /* VQRDMULH scalar */
if (u && ((rd | rn) & 1)) {
@@ -5212,41 +5208,14 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
} else {
gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp,
tmp2);
}
- } else if (op == 13) {
+ } else {
if (size == 1) {
gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp,
tmp2);
} else {
gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp,
tmp2);
}
- } else {
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- gen_helper_vfp_muls(tmp, tmp, tmp2, fpstatus);
- tcg_temp_free_ptr(fpstatus);
}
tcg_temp_free_i32(tmp2);
- if (op < 8) {
- /* Accumulate. */
- tmp2 = neon_load_reg(rd, pass);
- switch (op) {
- case 1:
- {
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
- tcg_temp_free_ptr(fpstatus);
- break;
- }
- case 5:
- {
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- gen_helper_vfp_subs(tmp, tmp2, tmp, fpstatus);
- tcg_temp_free_ptr(fpstatus);
- break;
- }
- default:
- abort();
- }
- tcg_temp_free_i32(tmp2);
- }
neon_store_reg(rd, pass, tmp);
}
break;
--
2.20.1
- [PULL 01/23] target/arm: Fix missing temp frees in do_vshll_2sh, (continued)
- [PULL 01/23] target/arm: Fix missing temp frees in do_vshll_2sh, Peter Maydell, 2020/06/16
- [PULL 02/23] target/arm: Convert Neon 3-reg-diff prewidening ops to decodetree, Peter Maydell, 2020/06/16
- [PULL 03/23] target/arm: Convert Neon 3-reg-diff narrowing ops to decodetree, Peter Maydell, 2020/06/16
- [PULL 04/23] target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree, Peter Maydell, 2020/06/16
- [PULL 05/23] target/arm: Convert Neon 3-reg-diff long multiplies, Peter Maydell, 2020/06/16
- [PULL 06/23] target/arm: Convert Neon 3-reg-diff saturating doubling multiplies, Peter Maydell, 2020/06/16
- [PULL 07/23] target/arm: Convert Neon 3-reg-diff polynomial VMULL, Peter Maydell, 2020/06/16
- [PULL 08/23] target/arm: Add 'static' and 'const' annotations to VSHLL function arrays, Peter Maydell, 2020/06/16
- [PULL 09/23] target/arm: Add missing TCG temp free in do_2shift_env_64(), Peter Maydell, 2020/06/16
- [PULL 10/23] target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree, Peter Maydell, 2020/06/16
- [PULL 11/23] target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree,
Peter Maydell <=
- [PULL 13/23] target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree, Peter Maydell, 2020/06/16
- [PULL 12/23] target/arm: Convert Neon 2-reg-scalar VQDMULH, VQRDMULH to decodetree, Peter Maydell, 2020/06/16
- [PULL 14/23] target/arm: Convert Neon 2-reg-scalar long multiplies to decodetree, Peter Maydell, 2020/06/16
- [PULL 15/23] target/arm: Convert Neon VEXT to decodetree, Peter Maydell, 2020/06/16
- [PULL 16/23] target/arm: Convert Neon VTBL, VTBX to decodetree, Peter Maydell, 2020/06/16
- [PULL 18/23] hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers, Peter Maydell, 2020/06/16
- [PULL 19/23] Implement configurable descriptor size in ftgmac100, Peter Maydell, 2020/06/16
- [PULL 20/23] target/arm/cpu: adjust virtual time for all KVM arm cpus, Peter Maydell, 2020/06/16
- [PULL 21/23] hw/net/imx_fec: Convert debug fprintf() to trace events, Peter Maydell, 2020/06/16
- [PULL 23/23] hw: arm: Set vendor property for IMX SDHCI emulations, Peter Maydell, 2020/06/16