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Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 |
Date: |
Thu, 18 Jun 2020 23:04:57 -0700 |
On Wed, Jun 17, 2020 at 10:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Alistair,
>
> On Thu, Jun 18, 2020 at 8:41 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Alistair,
> >
> > On Thu, Jun 18, 2020 at 12:40 AM Alistair Francis <alistair23@gmail.com>
> > wrote:
> > >
> > > On Mon, Jun 15, 2020 at 5:51 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > >
> > > > From: Bin Meng <bin.meng@windriver.com>
> > > >
> > > > Per the SiFive manual, all E/U series CPU cores' reset vector is
> > > > at 0x1004. Update our codes to match the hardware.
> > > >
> > > > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > >
> > > This commit breaks my Oreboot test.
> > >
> > > Oreboot starts in flash and we run the command with the
> > > `sifive_u,start-in-flash=true` machine.
> >
> > Could you please post an Oreboot binary for testing somewhere, or some
> > instructions so that I can test this?
> >
>
> I have figured out where the issue is. The issue is inside the Oreboot
> codes that its QEMU detecting logic should be updated to match this
> change.
>
> I've sent pull request to Oreboot to fix this:
> https://github.com/oreboot/oreboot/pull/264
Thanks for that.
>
> > >
> > > I have removed this and the later patches from the RISC-V branch. I
> > > want to send a PR today. After that I'll look into this.
> >
>
> I don't think we should drop this patch and later ones in this series.
Applied again then.
Alistair
>
> Regards,
> Bin
[PATCH v2 3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Bin Meng, 2020/06/15
[PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries, Bin Meng, 2020/06/15
[PATCH v2 5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Bin Meng, 2020/06/15
Re: [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support, Alistair Francis, 2020/06/16