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[PULL 21/32] hw/riscv: sifive_gpio: Clean up the codes
From: |
Alistair Francis |
Subject: |
[PULL 21/32] hw/riscv: sifive_gpio: Clean up the codes |
Date: |
Thu, 18 Jun 2020 23:25:07 -0700 |
From: Bin Meng <bin.meng@windriver.com>
Do various minor clean-ups to the exisiting codes for:
- coding convention conformance
- remove unnecessary blank lines
- spell SiFive correctly
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-6-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_gpio.h | 7 ++++---
hw/riscv/sifive_gpio.c | 13 +++++--------
2 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
index fce03d6c41..ad915b26d6 100644
--- a/include/hw/riscv/sifive_gpio.h
+++ b/include/hw/riscv/sifive_gpio.h
@@ -1,5 +1,5 @@
/*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
*
* Copyright 2019 AdaCore
*
@@ -10,10 +10,12 @@
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*/
+
#ifndef SIFIVE_GPIO_H
#define SIFIVE_GPIO_H
#include "hw/sysbus.h"
+
#define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
#define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
@@ -66,7 +68,6 @@ typedef struct SIFIVEGPIOState {
uint32_t out_xor;
uint32_t in;
uint32_t in_mask;
-
} SIFIVEGPIOState;
-#endif
+#endif /* SIFIVE_GPIO_H */
diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 5c7c596e6b..c9cffa2eba 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -1,5 +1,5 @@
/*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
*
* Copyright 2019 AdaCore
*
@@ -20,7 +20,6 @@
static void update_output_irq(SIFIVEGPIOState *s)
{
-
uint32_t pending;
uint32_t pin;
@@ -186,7 +185,7 @@ static uint64_t sifive_gpio_read(void *opaque, hwaddr
offset, unsigned int size)
}
static void sifive_gpio_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned int size)
+ uint64_t value, unsigned int size)
{
SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
@@ -318,7 +317,6 @@ static void sifive_gpio_reset(DeviceState *dev)
s->out_xor = 0;
s->in = 0;
s->in_mask = 0;
-
}
static const VMStateDescription vmstate_sifive_gpio = {
@@ -342,8 +340,8 @@ static const VMStateDescription vmstate_sifive_gpio = {
VMSTATE_UINT32(iof_en, SIFIVEGPIOState),
VMSTATE_UINT32(iof_sel, SIFIVEGPIOState),
VMSTATE_UINT32(out_xor, SIFIVEGPIOState),
- VMSTATE_UINT32(in, SIFIVEGPIOState),
- VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
+ VMSTATE_UINT32(in, SIFIVEGPIOState),
+ VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
VMSTATE_END_OF_LIST()
}
};
@@ -356,7 +354,6 @@ static void sifive_gpio_init(Object *obj)
TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
-
for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
}
@@ -371,7 +368,7 @@ static void sifive_gpio_class_init(ObjectClass *klass, void
*data)
dc->vmsd = &vmstate_sifive_gpio;
dc->reset = sifive_gpio_reset;
- dc->desc = "sifive GPIO";
+ dc->desc = "SiFive GPIO";
}
static const TypeInfo sifive_gpio_info = {
--
2.27.0
- [PULL 00/32] riscv-to-apply queue, Alistair Francis, 2020/06/19
- [PULL 15/32] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/06/19
- [PULL 02/32] sifive_e: Support the revB machine, Alistair Francis, 2020/06/19
- [PULL 04/32] riscv: Generalize CPU init routine for the gcsu CPU, Alistair Francis, 2020/06/19
- [PULL 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL 16/32] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/06/19
- [PULL 14/32] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/06/19
- [PULL 06/32] riscv: Keep the CPU init routine names consistent, Alistair Francis, 2020/06/19
- [PULL 21/32] hw/riscv: sifive_gpio: Clean up the codes,
Alistair Francis <=
- [PULL 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/19
- [PULL 01/32] riscv: Add helper to make NaN-boxing for FP register, Alistair Francis, 2020/06/19
- [PULL 10/32] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/19
- [PULL 11/32] riscv/opentitan: Fix the ROM size, Alistair Francis, 2020/06/19
- [PULL 03/32] riscv: Generalize CPU init routine for the base CPU, Alistair Francis, 2020/06/19
- [PULL 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/06/19
- [PULL 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL 05/32] riscv: Generalize CPU init routine for the imacu CPU, Alistair Francis, 2020/06/19
- [PULL 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Alistair Francis, 2020/06/19
- [PULL 08/32] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/19